Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-08-23
2001-12-11
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S675000, C257S676000
Reexamination Certificate
active
06329706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a leadframe and a semiconductor package adopting the same, and more particularly, to a leadframe adopting a chip pad capable of dissipating heat produced by a chip, and a semiconductor package adopting the leadframe.
2. Description of the Related Art
Semiconductor devices are used for processing information or signals, in addition to controlling current or power in electric or electronic circuits. The semiconductor device in controlling current or power consumes a relatively high current or voltage compared to the device for information or signal processing. For this reason, the current or power controlling semiconductor device is referred to as a power device, as distinguished from general semiconductor devices.
Semiconductor packages in which such power devices are embedded produce a large amount of heat, because a high current flows through the semiconductor packages at a high operating voltage. To dissipate heat produced by a chip embedded in such a semiconductor package, a heat spreader or a heat slug is inserted below or attached to a chip mounting pad. Recently, the backside of the chip pad is directly exposed to the outside to dissipate heat, thereby reducing the production cost of semiconductor packages.
Such a technique of exposing the chip pad of the semiconductor package to the outside is described in U.S. Pat. No. 5,594,234 (entitled “Downset Exposed Die Mount Pad Leadframe and Package” and assigned to Texas Instruments Corp. on Jun. 14, 1997), and U.S. Pat. No. 5,440,269 (entitled “Resin-packaged Semiconductor Device with Flow Prevention Dimples” and assigned to Mitsubishi Denki Kabushiki Kaisha on Aug. 8, 1995).
FIG. 1
is a sectional view of a conventional semiconductor package issued to Texas Instruments Corp. Referring to
FIG. 1
, a chip
39
is attached to a chip pad
31
of a leadframe and molded into a semiconductor package using an epoxy mold compound (EMC)
40
. Reference numeral
36
represents leads, reference numeral
31
a
represents the bottom of the chip pad
31
, and reference numerals
34
and
35
represent wings which extend upward and outward from the chip pad
31
so as to increase the moisture path.
However, such a semiconductor package with wings causes flash on the bottom of the semiconductor package during the molding process with a molding material. In other words, the EMC flows over the bottom of the chip pad, so that a linear distinct boundary line cannot be formed between the exposed portion and the sealed portion of the chip pad. As a result, the exposed portion of the bottom surface of the chip pad cannot be formed to have a trim rectangular outline, and instead has an irregular outline because of the flowed molding material. Since the flowed molding material covers the bottom of the chip pad, which serves as the heat conducting path, the heat dissipating effect of the chip pad is lowered. To solve this problem, an additional deflash process must be carried out on the semiconductor package after the molding process is completed. The deflash process means the process of dipping the semiconductor package in a solution to dissolve and remove the unnecessary flowed molding material from the bottom of the chip pad. In addition, such a semiconductor package having the chip pad exposed to the outside is susceptible to thermal stress.
FIG. 2
is a sectional view of another conventional semiconductor package assigned to Mitsubishi Denki Kabushiki Kaisha, and
FIG. 3
is a bottom view of the semiconductor package of FIG.
2
.
Referring to
FIGS. 2 and 3
, dimples
25
are formed on the bottom
2
b
of the chip pad
2
a
to prevent flashing during molding with a molding material. Also, the edge of the chip pad is completely surrounded with the molding material, which increases the moisture path. However, a step between the bottom
2
b
of the chip pad
2
a
and the bottom of the molding material hinder direct contact with a printed circuit board (PCB)
30
, and the reduction of the bottom area of the chip pad by the molding material, lowers the heat dissipating efficiency. In
FIGS. 2 and 3
, reference numeral
3
represents epoxy for attaching a chip
1
to a chip pad
2
a,
reference numeral
4
represents a gold wire, reference numeral
5
represents an inner lead, reference numeral
6
represents an EMC, reference numeral
7
represents an outer lead, and reference numeral
30
represents a PCB on which the semiconductor package is mounted.
However, the semiconductor package with dimples cannot suppress flashing at non-dimple portions of the semiconductor package, and deteriorates heat dissipating characteristics. In addition, since the chip pad of the semiconductor package directly contacts the PCB, the chip pad is susceptible to thermal stress.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a semiconductor package adopting a chip pad as a heat conducting path, which can effectively restrict moisture intrusion into the semiconductor package, and effectively prevent flush on the bottom of the semiconductor package during a molding process, and reduce thermal stress caused by heat produced by the chip pad.
It is another objective of the present invention to provide a leadframe for use in the semiconductor package.
The first objective of the present invention is achieved by a semiconductor package comprising: a leadframe including inner lead, outer lead, and a chip pad, the outer leads being correspondingly connected to the inner leads of the leadframe, extending out of the semiconductor package, the chip pad having a first surface on which a chip is mounted, and a second surface which is opposite to the first surface and is partially exposed to the outside of the semiconductor package, a chip mounted on the first surface of the chip pad and sealed by epoxy, gold wires for connecting bonding pads of the chip to corresponding inner leads of the leadframe, and an epoxy mold compound (EMC) covering the first surface of the chip pad and inner leads, but exposing a portion of the second surface of the chip pad. In the leadframe of the semiconductor package, the chip pad comprises: at least two swaged portions formed along edges of the chip pad of the leadframe; a first narrow and long groove formed on the first surface of the chip pad of the leadframe along the edge thereof; a second narrow and long groove formed on the second surface of the chip pad of the leadframe along the edge thereof, not to be covered with the EMC; and at least one slot formed in the chip pad of the leadframe.
Preferably, the swaged portions are formed on the second surface of the chip pad.
Preferably, the second groove on the second surface of the chip pad has a V-like shape or a U-like shape, and is formed to be exposed to the outside of the semiconductor package, along the four sides of the chip pad in a rectangular shape.
Preferably, the first groove on the first surface of the chip pad has a V-like shape or a U-like shape, and is formed along the outline of a chip mount area on the first surface of the chip pad in a rectangular shape.
Preferably, the plurality of slots are formed in the chip pad of the leadframe surrounding a chip mount area, and the plurality of slots are separated from each other, and wings are formed near the slots in the chip pad of the leadframe, by bending upward and outward a portion of the chip pad. The wings near the at least one slot in the chip pad of the leadframe may be adjacent to a chip mount area.
The second objective of the present invention is achieved by a leadframe comprising: a chip pad having a first surface on which a chip is mounted, and a second surface which is opposite to the first surface and is partially exposed to the outside of the semiconductor package; and a plurality of leads extending out from the chip pad, a portion of the leads being molded with an epoxy mold compound (EMC) and the other portion of the leads extending outside a semiconductor package. The chip pad of
Fairchild Korea Semiconductor Ltd.
Potter Roy
Rothwell, Figg, Ernst & Manbeck pc
LandOfFree
Leadframe using chip pad as heat conducting path and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Leadframe using chip pad as heat conducting path and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leadframe using chip pad as heat conducting path and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2569415