Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1998-05-06
2002-05-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S667000, C257S669000, C257S676000, C257S709000, C257S725000, C257S788000, C257S796000
Reexamination Certificate
active
06384478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor packaging, and more particularly to a leadframe having a paddle area containing an electrically isolated region.
2. Description of Related Art
The electronics industry has continued to make significant advances in microelectronics technology. These advances are producing silicon-based integrated circuits with increased circuit density and a corresponding rise in the rate at which functions are performed. However, as circuit density and speed are improved, corresponding progress must be made with the structures that carry the device and provide the input/output (I/O) interconnections.
The structure that carries a semiconductor device and provides the necessary I/O interconnections is generally referred to as the package. A typical microelectronic package is designed to provide a structure to support and protect the device and a means by which to distribute circuit generated heat. Furthermore, the package provides connections for signal lines leading onto and out of the silicon chip, connections that present varying potentials for power and ground, and a wiring structure for I/O signal interconnections within a system. These connections must be made at each level of the packaging hierarchy and as this hierarchy is traversed (i.e., from the chip to the I/O components), connection scaling must be provided because the circuits and connections (i.e., wire lines) continue to increase in size. At the first level of the hierarchy (i.e., chip to substrate), this scaling is usually provided by the leadframe.
A plan view of a conventional leadframe
20
is shown in
FIG. 1 and a
cross-sectional view of the leadframe
20
taken along lines
2
—
2
of
FIG. 1
is presented in FIG.
2
. Referring to FIG.
1
and
FIG. 2
, the leadframe
20
has a leadframe body
22
that contains a die-mounting structure
24
. The die-mounting structure
24
is typically formed through an etching or stamping process and the leadframe is usually made of a metal, such as copper (Cu) or a metal alloy.
The die-mounting structure
24
has a square die-pad or paddle
26
for receiving a semiconductor chip
28
that may be adhesively or metallurgically bonded thereon and four structural supports
30
,
32
,
34
,
36
. Each of the structural supports
30
,
32
,
34
,
36
extend from a corresponding corner of the paddle
26
so that the paddle
26
is mechanically connected to the leadframe body
22
.
The die-mounting structure also has numerous leads
38
,
40
that provide the scaled connections from the chip
28
to the next level of the package. The leads
38
,
40
are commonly connected to the chip
28
using a process called wire bonding. This process consists of attaching flexible wires
42
,
44
from the chip bonding pads
46
,
48
to the lead posts
50
,
52
, or alternatively, from the chip bonding pads
46
,
48
to the paddle
26
.
Currently, 25% to 40% of the leads are assigned to different ground and power supply nets. Therefore, power supply and ground contacts have a major contribution to package cost, size, and performance. Furthermore, path inductance from the chip to the outside of the package, which is directly proportional to the path length from the bond pads of the chip to the bond pads of the leads, continues to negatively impact chip performance, especially for digital/mixed signal and Radio Frequency (RF) chips. While a leadframe based package with a low inductive path is currently available in a deep down-set paddle package, only a single low inductive path is provided and typically used for ground.
An additional packaging limitation is the inability to effectively integrate high Q inductors. As inductors with values ranging from 1.5 nH to 15 nH and having a Q greater than 20 are used in Voltage Controlled Oscillators (VCO), input and output matching of Low Noise Amplifiers (LNA), output matching RF circuit mixers, and gain adjustment circuits, integration of high Q inductors into a microelectronic package is highly desirable. However, the current practice of using on-chip inductors fails to provide an adequate solution.
On-chip inductors are usually limited to low Q values (i.e., typically less than 5). Furthermore, on-chip inductors tend to couple noise through the substrate. In addition, creation of on-chip inductors requires a thick metal layer (i.e., usually greater than 2 microns) which consumes a significant area of the chip and reduces chip yield while increasing chip cost. Therefore, an off-chip inductor would be preferable if a high Q was provided and the overall size of the microelectronic package was not significantly increased.
In view of the foregoing, it is an object of the present invention to provide a leadframe that reduces the number of leads required for power supply and ground contacts, thereby reducing package cost, size, and performance. It is a further object of the present invention to reduce the path inductance from the semiconductor device to the outside of the package for power supply, ground and I/O interconnections, especially for high speed signals that have data rates of at least one gigabit/second. In addition, it is an object of the present invention to provide an off-chip inductor having a high Q without significantly increasing the overall size of the package. Furthermore, additional advantages and features of the present invention will become apparent from the subsequent description and claims taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
A leadframe for a semiconductor device is provided that includes a leadframe body and a paddle area within the leadframe body for mounting the semiconductor device thereon. The leadframe also has an electrically isolated region within the paddle area.
A method of forming an isolated region in a paddle of a leadframe is provided that includes defining a first region within the paddle and a second region within the leadframe with the first region demarcating the isolated region within the paddle and the second region designating a support region of the isolated region. The method also has the steps of removing base material of the paddle that is adjacent to the first region such that a gap is formed around a substantial portion of the first region and the second region remains at least partially connected to said first region. The second region is disconnected from the first region such that the first region is isolated from the second region and isolated within the paddle.
Additional advantages and features of the present invention will become apparent from the subsequent description and claims taken in conjunction with the accompanying drawings.
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patent: 5294867 (1994-03-01), Notani et al.
patent: 5428245 (1995-06-01), Lin et al.
patent: 5442228 (1995-08-01), Pham et al.
patent: 5504370 (1996-04-01), Lin et al.
patent: 5508556 (1996-04-01), Lin
patent: 6034423 (2000-02-01), Mostafazadeh et al.
patent: WO 96 08842 (1996-03-01), None
Patent Abstracts of Japan, vol. 096, No. 004, Apr. 30, 1996 & JP 07 321069 A (NEC Corp.) Dec. 8, 1995.
Patent Abstracts of Japan, vol. 015, No. 405, Oct. 16, 1991 & JP 03 166756 A (Seiko Epson Corp.) Jul. 18, 1991.
Patent Abstracts of Japan, vol. 018, No. 617, Nov. 24, 1994 & JP 06 236959 A (Ibiden Co. Ltd.) Aug. 23, 1994.
Walter Marton, Ansgar Pottbäcker, “Coil in Leadframe,” IEEE Workshop on Chip Package Co-Design CPD '98, ETH Zurich, Switzerland, Mar. 24, 1998.
Conexant Systems Inc.
Lee Eddie
Thomas, Kayden Horstmeyer & Risley
Warren Matthew E.
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