Leadframe-based chip scale semiconductor packages

Details Leadframe-based chip scale semiconductor packages Leadframe-based chip scale semiconductor packages

2011-05-17

2011-05-17

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With separate tie bar element or plural tie bars

C257S666000, C257S672000, C257S723000, C257S724000, C257SE23031, C257SE23037, C257SE23043, C257SE23046, C438S123000

Reexamination Certificate

active

07944031

ABSTRACT:
Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described.

REFERENCES:
patent: 2008/0272472 (2008-11-01), Hata et al.
ROHM GMD2 Product Brochure, www.rohm.com/ad/gmd2/, (last accessed Mar. 16, 2009).

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