Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With separate tie bar element or plural tie bars
Reexamination Certificate
2000-11-02
2002-11-19
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With separate tie bar element or plural tie bars
C257S666000
Reexamination Certificate
active
06483177
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to leaded semiconductor packages d a method of trimming and singulating such packages using a panel with a plurality of lead frames.
BACKGROUND
Conventionally, formation of a leaded semiconductor package begins by mounting a semiconductor die to a lead frame. The mounting generally includes attaching the semiconductor die to a mounting paddle of the lead frame and wire bonding electrical contacts of the semiconductor die to leads of the lead frame. Upon mounting as such, the semiconductor die is molded with a protective cover to prevent contamination or to alleviate damage to the semiconductor die. The protective cover may be provided with, for example, an epoxy resin that requires a curing process. After the curing process, formation of the leaded semiconductor package is completed when the leads are trimmed and formed by, for example, punching to separate undesired portions of a lead frame.
Generally, a plurality of lead frames is arrayed on a panel so that more than one semiconductor die can be mounted for each panel. Following the formation steps described above, each semiconductor die is mounted onto a respective lead frame and molded together with other semiconductor dies on the panel. The panel is then trimmed and sawed to provide individual or singulated leaded semiconductor packages. Each of these singulated leaded semiconductor packages is functionally tested to check electrical performance of the semiconductor die mounted within.
In the above method to form a leaded semiconductor package, a mounting paddle supports a semiconductor die. However, other supporting materials such as, for example, an adhesive tape, can replace the mounting paddle to reduce thickness of the leaded semiconductor package. For example, U.S. Pat. No. 51286,679, issued to Farnworth et al on Feb. 15, 1994 and U.S. Pat. No. 5,729,049, issued to Corisis et al on Mar. 17, 1998, both assigned to Micron Technology, Inc., describe use of an adhesive tape in place of the mounting paddle. Also, U.S. Pat. No. 5,789,083, issued to Kinsman on Aug. 4, 1998 and assigned to Micron Technology, Inc., describes use of a support structure to support a semiconductor die during functional testing and that is removed during trim and form.
Although the above techniques are adopted to reduce the size of leaded semiconductor packages, further reduction in this size is likely to cause a problem in handling or transporting such packages. This is because existing equipment used in packaging and electrical testing requires modifications to accommodate smaller leaded semiconductor packages for such handling or transporting. These modifications can be expensive and are likely to incur development costs that increase the cost of a leaded semiconductor package.
In U.S. Pat. No. 5,926,380, issued to Kim on Jul. 20, 1999 and assigned to LG Semicon Co., Ltd., a lead frame lattice is used to assemble a plurality of integrated chips formed in a wafer. However, the integrated chips are sawn for functional testing and the problem described above still limits any reduction in the size of such integrated chips. Also, transport time to transport an integrated chip from a carrier to a test position and vice versa affects cycle time to form the integrated chip. Furthermore, lead-supporting bars of the lead frame lattice have to be sawn entirely to detach each of the plurality of integrated chips.
As consumer demands for smaller portable electronic devices increase, development of smaller leaded semiconductor packages helps to meet such demands. Therefore, in view of these consumer demands, a need clearly exists for a leaded semiconductor package that can be formed in a smaller size without being limited by existing equipment in terms of handling or transporting.
SUMMARY
In accordance with one aspect of the invention, there is disclosed a leaded semiconductor package comprising:
a plurality of semiconductor dies; and
a panel having lead frames arrayed in a plurality of frame strips for mounting the plurality of semiconductor dies, the panel including:
a peripheral frame;
a plurality of dam bars disposed within the peripheral frame;
a plurality of leads extending transversely from portions of the plurality of dam bars; and
a plurality of support bars extending transversely from other portions of the plurality of dam bars, wherein each of the plurality of support bars is non-contiguous between the plurality of dam bars;
wherein the plurality of semiconductor dies are mounted to the lead frames, the panel being trimmed to form the plurality of leads respectively associated with each of the lead frames of each of the plurality of frame strips,
further wherein the panel is sawed across the plurality of frame strips to singulate the lead frames and thereby form at least one of the leaded semiconductor package.
Optionally, opposite ends of. each of the plurality of frame strips can comprise at least one primary tie bar.
More optionally, each of the plurality of frame strips can comprise at least one mounting paddle, the at least one mounting paddle being disposed between the opposite ends.
Generally, adjacent ones of the at least one mounting paddle can be connected by a secondary tie bar.
More generally, the other portions of the plurality of dam bars can be disposed between adjacent lead frames.
Optionally, the panel can further include at least one slot disposed between at least one side of the peripheral frame and the lead frames.
More optionally, the panel can further include at least one slot disposed between adjacent ones of the plurality of frame strips.
In accordance with another aspect of the invention, there is disclosed a method of trimming and singulating leaded semiconductor packages, the method comprising the steps of:
mounting a plurality of semiconductor dies onto lead frames of a panel, the lead frames being arrayed in a plurality of frame strips, each of the lead frames having a plurality of leads;
trimming by punching the panel to form the plurality of leads for each of the lead frames; and
sawing across the plurality of frame strips to singulate the lead frames and thereby form the leaded semiconductor packages.
Generally, the sawing step can comprise the step of sawing along each of a plurality of support bars extending transversely from a plurality of dam bars, the plurality of dam bars being disposed within a peripheral frame of the panel.
Optionally, the method can further comprise the step of functionally testing one or more of the plurality of semiconductor dies mounted on the lead frames prior to the sawing step.
Generally, the mounting step can comprise the step of attaching an adhesive side of at least one single-sided adhesive tape to a planar side of the panel.
Optionally, the attaching step can comprise the step of aligning the at least one single-sided adhesive tape with each of the plurality of frame strips.
Generally, the mounting step can further comprise the step of affixing each of the plurality of semiconductor dies onto the adhesive side of the at least one single-sided adhesive tape.
More generally, the mounting step can further comprise the step of electrically connecting the plurality of semiconductor dies to the plurality of leads of respective the lead frames.
Optionally, the mounting step can further comprise the step of molding each of the plurality of semiconductor dies after the electrically connecting step.
More optionally, the mounting step can further comprise the step of removing the at least one single-sided adhesive tape after the molding step.
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Elms Richard
Smith Brad
ST Assembly Test Services Ltd
Wood Phillips Katz Clark & Mortimer
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