Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2001-01-26
2004-09-14
Berman, Susan (Department: 1711)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S504000, C427S510000, C427S514000, C438S780000, C438S795000, C522S083000, C522S077000, C522S066000, C522S174000
Reexamination Certificate
active
06790473
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to low profile electronic circuit package structures and particularly to such packages for use within light weight, portable devices.
BACKGROUND OF THE INVENTION
Electronic package assemblies which utilize various organic substrates (e.g., printed circuit boards comprised of epoxy resin or the like material) having one or more electronic packages surface mounted thereon are known. These electronic packages include a relatively flat housing component having therein at least one semiconductor device (integrated circuit chip). This semiconductor device is, in turn, electrically connected to various conductive leads (e.g., copper) which project therefrom. One first level package known in the art is a dual in-line package (DIP). The integrated circuit chips embedded within such integrated circuit chip packages provide various functions (e.g., memory, logic, connectivity) for the overall system. The conductive leads which project from these packages are electrically coupled to respective conductor pads (e.g., copper) or the like which may form the circuitry on an upper surface of the organic substrate. Various solder compositions may be used to provide individual connections between respective pairs of leads and conductors.
Recently, there have been developed integrated circuit chip packages of relatively low profile which include an insulative housing of relatively thin construction. Such packages are referred to in the art as TSOP's, standing for Thin Small Outline Package. Such devices, being thin, occupy a minimum of height on the respective organic substrate and are further capable of being surface mounted to the substrate's respective circuitry (e.g., conductor pads) using known (e.g., soldering) techniques. These relatively new packages include memory, logic, and connectivity integrated circuit chips as the semiconductor devices thereof. Significantly, these recently developed packages are able to provide such functioning while assuring a compact, low profile, thus representing a substantial savings in space for the final product utilizing same. These surface mounted Thin Small Outline Packages result in a particularly thin total package of substrate and chips mounted thereon. The resulting packages, exemplified by PCMCIA cards, are preferred for portable computers, entertainment systems, and telecommunications handsets.
“PCMCIA” stands for the Personal Computer Memory Card International Association. PCMCIA cards are the “credit card” peripherals used as memory cards, including DRAM, SRAM, ROM, and PROM cards, modem-fax cards, mini-hard drive cards, terminal emulator cards, and the like. They are built to a PCMCIA standard. The PCMCIA standard sets the electrical, mechanical, and interface requirements for PCMCIA cards.
The small size of PCMCIA cards is intended to meet the form factor demands of portable computers. These small cards are approximately the size of a plastic credit card but several times thicker (Type I PCMCIA cards are 3.3 mm thick, Type II PCMCIA cards are 5 mm thick). It should be noted that, as used herein, Type I and Type II refer to the PCMCIA form and fit type standards, and not to the method of surface mount device attachment. PCMCIA cards are described in, for example, R. C.
Alford, “Under The Hood: The PCMCIA Redefines Portability”,
Byte Magazine
, Dec. 1992, pp. 237-242; by Ken Ueltzen “Pushing The Packaging Envelope”,
Circuit Assembly
, Mar. 1992, pp. 32-35, and Richard Nass, “IC-Card Spec Adapts I/O To Memory Card Slot,” Electronic Design. Jan. 22, 1992, pp. 45-57.
The Type I PCMCIA card itself is 3.3 millimeters thick from top cover to bottom cover, with the top cover and bottom cover having a total combined thickness of just 0.4 millimeters. This allows 2.9 millimeters of thickness for a populated, double sided, printed circuit card.
The height limitations of Type I cards, 3.3 mm, requires the use of low profile technologies, for example, either tape automated bonding (TAB) or card-on-board (COB) packaging technologies, both with specially designed low height IC chips, as TSOP IC chips. The thin, small outline package (TSOP) IC chip, with a height of 1.2 mm (0.047 inch), is particularly desirable for double sided Type I PCMCIA cards. Its low profile allows population of both sides of the PCMCIA printed circuit card.
In an alternative IC chip technology a paper thin small outline package (PTSOP) having a height of just 0.5 mm (0.020 inch) is utilized, allowing two printed circuit cards to be carried in a single PCMCIA card package. The lead pitch for TSOP IC chips is 0.5 mm (0.019 inch). Memory printed circuit cards are populated with 0.019 inch to 0.025 inch lead pitch IC chips, with approximately 1000 solder joints per printed circuit card.
It has been found that when TSOP packages, as well as similar thin packages, are surface mounted on organic substrates (and particularly those of epoxy resin or perfluorocarbon dielectric material) of relatively thick configuration (e.g., greater than about 0.050 inches thick), relatively significant thermal stress is placed on the solder-lead joints, which thermal stress can in turn adversely effect such joints, possibly causing separation thereof. Such resulting separation may cause disconnection between the lead and solder, thereby rendering the total package inoperative. Such thermal stress is caused during operation of the package as a result of relatively substantial differences in the coefficients of thermal expansion (CTE) of the organic substrate and the coefficients of expansion (CTE) of various other elements (e.g., the conductive leads, solder and package housing). Such differences are even more pronounced when thicker multi-layer organic substrates (e.g., those including several conductive layers therein which function as signal, power or ground planes) are utilized. Multilayer substrates are often desired in the computer, electronics, and telecommunications industries in order to provide additional functioning within a single package, especially a package containing a plurality of multi-function integrated circuit chips.
A clear need exists for an electronic package assembly which permits the utilization of electronic packages such as those of the TSOP variety to be effectively utilized on organic substrates, and particularly multilayer substrates.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to enhance the electronic package assembly art.
It is another object of the invention to provide an electronic package assembly which obviates the aforementioned thermal stress problem.
It is yet another object of the invention to provide such a package which can be produced on a relatively large scale, to thus benefit from the several advantages (e.g., lower cost) associated therewith.
It is yet a further object of the invention to provide a photopolymerized resin, formed of an epoxy resin or a cyanate monomer, a photoinitiator, and a dispersed phase of particulate silica, that is useful to obviate the aforementioned thermal stress problem in electronic circuit packages.
In accordance with one aspect of the invention, there is provided an electronic package assembly which comprises an organic substrate including a surface thereon having a plurality of electrical conductors positioned on the surface, an electronic package including an insulative integrated circuit chip housing located on or above the substrate's surface and including sides which include a plurality of conductive leads projecting therefrom, individual quantities of solder for substantially covering respective pairs of one such lead and a respective conductor, and encapsulant material located on these quantities of solder for substantially covering the solder so as to substantially prevent electrical disconnection between the conductive leads and the solder during operation of the electronic package assembly.
Encapsulant compositions are also disclosed in accordance with the invention. The encapsulant compositions include an epoxy re
Cangelosi Joan
Dittrich Deborah L.
Fuerniss Stephen J.
Papathomas Konstantinos I.
Wang David W.
Berman Susan
Cangelosi Joan
Schmeiser Olsen & Watts
Steinberg William H.
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