Lead-on chip semiconductor device having peripheral bond pads

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

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Details

257670, 257674, 257676, H01L 2348, H01L 2944, H01L 2952, H01L 2960

Patent

active

053810368

ABSTRACT:
A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

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". . . 2 . . . 16 M DRAM . . . LOC . . . ," published in Nikkei MicroDevices in Nov., 1991, pp. 79-83 (Full Translation on order and will be provided upon receipt by Applicant).
"DRAM, SRAM . . . LOC . . . 16M DRAM, 4M . . . SRAM . . .," published in Nikkei MicroDevices in Feb., 1992, pp. 77-84 (Full Translation on order and will be provided upon receipt by Applicant).
"Packaging Technology for Thin, High Density and High Speed Devices," by G. Murakami et al., Hitachi Review, vol. 40, No. 1, Feb. 1991, pp. 51-56.

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