Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-05-26
2003-09-02
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S668000, C257S673000, C257S674000
Reexamination Certificate
active
06614101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a small thin plastic packaged semiconductor device having electrode pads in a central area of an upper surface of a semiconductor chip and, more particularly, to a lead frame capable of achieving the wire bonding of high reliability by preventing the contact of bonding wires to a chip edge and a semiconductor device using the same.
2. Description of the Related Art
In recent years, reduction in size and thickness is required of the semiconductor device more and more with the increase in integration and function, and thus the technological developments therefor proceed. Especially, in the fields such as the memory card, the memory module, etc. in which the high density packaging is requested, the request for reduction in size and thickness of the package is being made strongly. The package standard based on TSOP (Thin Small Out-line Package) standard is widely employed at present, nevertheless further reduction in size and thickness of the package is required.
One of the problems caused when the reduction in size and thickness of the plastic packaged semiconductor device advances is that the bonding wire comes into contact with the edge of the semiconductor chip. Various improvements have been made to prevent this problem. For example, in Japanese Patent Unexamined Publication No. Hei. 5-121635, in such a semiconductor device that the inner leads are arranged in close vicinity of the electrode pads which are located on the surface of the upper end portion of the semiconductor chip, an improved lead frame is disclosed. That is, since a height of the upper surfaces of the inner leads to which the wires are connected is set equally to surfaces of the electrode pads of the semiconductor chip mounted on the die pad to eliminate difference in level between them, the wire bonding can be applied to such lead frame not to bring the wires into contact with the edge of the semiconductor chip even when deformation, dip, etc. are caused in the short wire or the long wire.
Also, in Japanese Patent Unexamined Publication No. Hei. 10-56032, as such a semiconductor device that the inner Leads are arranged in close vicinity of the electrode pads in which the electrodes of the semiconductor chip are arranged on the surface of the upper end portion of the chip, an improved semiconductor device is disclosed. That is, in the semiconductor device which includes the die pad, the semiconductor chip, the lead frame, the bonding wires, and the molding plastic, since a level of the die pad can be lowered such that the height of the upper surfaces of the inner leads and a height of the upper surfaces of the bonding wire balls are set to a substantially identical level, deformation of the bonding wire balls during the wire bonding and deformation and cutting of the bonding wires at the boundary between the bonding wires and the bonding wire balls can be prevented, and thus the bonding wires are in no way brought into contact with the edge of the semiconductor chip.
As described above, the plastic packaged semiconductor devices in the related art have constructed to overcome the technological subjects caused to reduce the thickness of the package in which the inner leads are arranged in close vicinity to the electrode pads being arranged on the surface of the upper end portion of the semiconductor chip. In other words, in such semiconductor device that the inner leads are arranged in close vicinity to the electrode pads being arranged on the surface of the upper end portion of the semiconductor chip, since a bending curve of the bonding wires becomes sharp when the loop length is set short and the loop height is formed low, an excessive force is applied to the recrystallized portion of the bonding wires located immediately over the bonding wire balls, whereby the deformation or cutting of the bonding wires is easily caused. The above plastic packaged semiconductor devices in the related art can overcome these disadvantages and also can prevent the event that the bonding wires come into contact with the edge of the semiconductor chip because of the deformation or dip of the wire. However, even if these technological subjects can be overcome according to the above configuration, the plastic packaged semiconductor devices in the related art are not yet enough to answer the request for the further size reduction of the plastic packaged semiconductor device, which is requested in the market.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the above-mentioned problems, and it is an object of the present invention to provide a lead frame of high reliability and a plastic packaged semiconductor device using the same, which are capable of reducing a thickness and a size of the package, preventing not only deformation or cutting of bonding wires but also contact of the bonding wires to an edge of a semiconductor chip, and bringing about no reduction in production yield because of the exposure of the bonding wires and a die pad in plastic packaging, by using a semiconductor chip in which an electrode pad is arranged on an upper surface of a central portion, which has a high integration density, of the semiconductor chip in place of a semiconductor chip in which the electrode pad is arranged on the upper surface of the end portion of the semiconductor chip.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a lead frame comprising: a die pad on which a semiconductor chip having an electrode pad in a central portion of an upper surface is die-bonded; lifted leads which support the die pad; and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces, which are in parallel with a surface of the die pad and to which bonding wires are connected, wherein the upper flat surfaces of the tip portions of the inner leads are arranged more highly than the upper surface of the semiconductor chip by at least a dimension which is equivalent to a diameter of the bonding wires.
According to a second aspect of the present invention, there is provided a lead frame comprising: a die pad on which a semiconductor chip having an electrode pad in a central portion of an upper surface is die-bonded; lifted leads which support the die pad; and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces, which are in parallel with a surface of the die pad and to which bonding wires are connected, wherein the upper flat surfaces of the tip portions of the inner leads are arranged at a substantially same height as a maximum lifting height of the bonding wires which are connected to the electrode pad, then lifted to form a loop, and then connected to the upper flat surfaces.
According to a third aspect of the present invention, there is provided a plastic packaged semiconductor device comprising: a semiconductor chip which has an electrode pad arranged in a central portion of an upper surface; a die pad to which the semiconductor chip is die-bonded; bonding wires connected to the electrode pad; inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces which are positioned at a level equal to or higher than an upper surface of the semiconductor chip and to which the bonding wires are connected; and a sealing plastic for sealing the semiconductor chip, the die pad, the bonding wires, and the inner leads.
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patent:
Horita Manabu
Michii Kazunari
Misumi Kazuyuki
Fahmy Wael
Ha Nathan W.
McDermott & Will & Emery
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