Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-09-08
2002-08-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S684000, C257S696000, C257S698000, C257S712000, C257S713000, C257S706000, C257S707000, C257S670000, C257S672000, C257S675000, C257S678000, C257S692000
Reexamination Certificate
active
06437427
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lead frame used for the fabrication of semiconductor packages and a semiconductor package fabricated using the lead frame. More particularly, the present invention relates to a lead frame for semiconductor packages, which is provided with a semiconductor chip mounting plate having a semiconductor chip mounting function and a heat discharge function.
2. Description of the Prior Art
Referring to
FIG. 1
, a typical structure of a lead frame for semiconductor packages is illustrated. As shown in
FIG. 1
, the lead frame, which is denoted by the reference numeral
1
′ and made of copper or an alloy thereof, is provided at each of four facing sides thereof with a plurality of leads
3
(in a quad-flat type). The lead frame
1
′ may also be provided with a plurality of leads
3
at each of only two facing sides thereof (in a bi-flat type). A semiconductor chip mounting plate
2
is provided at the central portion of the lead frame
1
′ inside the leads
3
in such a fashion that it has a chip mounting surface flush with the plane of the leads
3
or a plane slightly set down below the plane of the leads
3
. A semiconductor chip
5
is mounted on the chip mounting surface of the semiconductor chip mounting plate
2
. The semiconductor chip mounting plate
2
is supported by tie bars
4
extending outwardly from four corners of the semiconductor chip mounting plate
2
to four corresponding corners of the lead frame
1
, respectively.
Typically, semiconductor mounting plates are adapted only to mount a semiconductor chip thereon. In association with such a semiconductor mounting plate, a typical package structure is used in which the semiconductor mounting plate is buried in a molded resin seal in such a fashion that it is not exposed to the outside. However, in the case of the package structure of
FIGS. 1 and 2
in which the semiconductor mounting plate
2
is packaged while having a great down-set depth, the semiconductor mounting plate
2
may be exposed to the outside at its lower surface so that it also serves as a heat sink. In the latter structure, ground bonding wires
7
are typically bonded to the upper surface of the semiconductor chip mounting plate
2
, which has a heat discharge function in addition to its basic function, so that the semiconductor chip mounting plate
2
is grounded.
In such a semiconductor package, namely, the semiconductor package
10
′ of
FIG. 2
using the above mentioned conventional lead frame
1
′ of
FIG. 1
provided with the semiconductor chip mounting plate
1
having a heat discharge function, there is a relatively great difference between the level of the leads
3
and the level of semiconductor chip mounting plate
2
. As a result, the bonding wires
7
have an increased length. For this reason, the bonding wires
7
may be short-circuited when an interface peel-off may occur between the semiconductor chip mounting plate
2
and the molded resin seal
6
or when an impact is applied to the semiconductor chip mounting plate
2
. In this case, a degradation in the wire bonding quality and reliability occurs. Since the flat surface of the semiconductor chip mounting plate
2
is exposed to the outside in order to obtain a heat discharge effect, moisture may easily penetrate into the package
10
′ through the interface between the resin seal
6
and semiconductor chip mounting plate
2
. In addition, there is a reduction in the coupling strength of the semiconductor chip mounting plate
2
to the resin seal
6
. As a result, an interface peel-off phenomenon caused by thermal stress may more easily occur.
SUMMARY OF THE INVENTION
Therefore, a primary object of the invention is to provide a lead frame having a structure capable of inhibiting or reducing an interface peel-off phenomenon occurring between its semiconductor chip mounting plate, adapted to also serve as a heat sink, and a resin seal encapsulating the semiconductor chip mounting plate.
A secondary object of the invention is to provide a lead frame having a structure capable of preventing moisture from penetrating between its semiconductor chip mounting plate and a resin seal encapsulating the semiconductor chip mounting plate or reducing the penetration of moisture.
A third object of the invention is to provide a lead frame having a structure capable of reducing the length of ground bonding wires, thereby effectively reducing the possibility of the bonding wires to be short-circuited.
A fourth object of the invention is to provide a semiconductor package using the lead frame according to one of the primary through third objects of the invention.
The primary and secondary objects of the present invention can be accomplished by providing a lead frame having a semiconductor chip provided at its peripheral portion with at least one groove having a rectangular ring shape.
The third object of the present invention can be accomplished by providing a lead frame having a ground bridge bar arranged between the semiconductor chip mounting plate and the leads while having a rectangular ring shape.
The fourth object of the present invention can be accomplished by providing a semiconductor package fabricated using any one of the lead frames respectively accomplishing the primary through third objects of the present invention.
REFERENCES:
patent: 5723899 (1998-03-01), Shin
patent: 59-115547 (1984-07-01), None
patent: 60-210845 (1985-10-01), None
patent: 6-85132 (1994-03-01), None
patent: 7-231069 (1995-08-01), None
Amkor Technology Inc.
Flynn Nathan J.
Sefer Ahmed N.
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