Lead frame lattice and integrated package fabrication method app

Details Lead frame lattice and integrated package fabrication method app Lead frame lattice and integrated package fabrication method app

1997-05-06

1999-07-20

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361820, 361772, 361723, 361717, 257666, 257672, 257618, 257622, 257676, 257690, 257692, 257734, H05K 0330

Patent

active

059263806

ABSTRACT:
A lattice of a plurality of individual lead frames allows concurrent or simultaneous molding of a plurality of integrated chips formed in a wafer. The lattice includes a plurality of lead supporting bars arranged in rows and columns and a plurality of leads attached to corresponding ones of the plurality of supporting bars. The plurality of lead supporting bars align with chip partition lines defining each individual integrated chip formed in the wafer. During fabrication, a plurality of individual lead frames is correspondingly attached to a plurality of individual integrated chips formed in a wafer. A plurality of wires are bonded between the plurality of chip pads and the plurality of leads. The wafer is molded such that the plurality of individual lead frames, the plurality of wires, the first surface of the plurality of individual integrated chips and the plurality of chip pads are molded with an epoxy compound with portions of the plurality of leads exposed. The wafer is cut along chip partition lines defining each individual chip to form a plurality of individual chip packages.

REFERENCES:
patent: 5363279 (1994-11-01), Cha
patent: 5554886 (1996-09-01), Song
patent: 5656553 (1997-08-01), Leas et al.
patent: 5657206 (1997-08-01), Pedersen et al.
patent: 5668400 (1997-09-01), Quinn
patent: 5685885 (1997-11-01), Khandros et al.

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