Lead frame for handling crossing bonding wires

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame

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257666, 257668, 257692, 257776, H01L 23495, H01L 2348, H01L 2352, H01L 2940

Patent

active

055856675

ABSTRACT:
A method is disclosed for packaging for an integrated circuit having lead frames with closely spaced leads that are configured in such a way that the bonding wires must cross over other leads prior to bonding to the appropriate lead. The method includes the formation of a modified lead frame such that the likelihood of electrical contact between the bonding wires and leads crossed over by bonding wires is reduced. In one embodiment, insulating film is placed on an adjacent lead, or additionally on a number of crossed over leads, directly under the path of the bonding wire such that the potential for electrical contact is reduced. In a second embodiment, a depression is formed on an adjacent lead, or additionally on a number of crossed over leads, causing additional clearance is created between the bonding wire and the lead such that the likelihood of contact is reduced. In a third embodiment, a stepped depression is formed on the bonded lead such that the depression facilitates the bonding of the wire at an increased incline resulting in additional space between bonding wire and the crossed leads thereby reducing the likelihood of contact.

REFERENCES:
patent: 3518504 (1967-10-01), Dietcrich
patent: 5072280 (1991-12-01), Matsukura
patent: 5086018 (1992-02-01), Conru et al.
patent: 5229329 (1993-07-01), Chai et al.
patent: 5455452 (1995-10-01), Kiyono
IBM Technical Disclosure Bulletin, vol. 34 No. 1, Jun. 1991 New York US, pp. 358-359. "Thin Small Outlene Packages".
Patent Abstracts Of Japan vol. No. 061 (E-1316), 5 Feb. 1993 & JP, A 04 267534 (NEC Kyushu Ltd) 24 Sep. 1992.
Patent Abstracts Of Japan vol. 016 No. 055 (E-1165), 12 Feb. 1992 & JP, A 03 255655 (NEC Corp) 14 Nov. 1991.

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