Lead frame for a semiconductor integrated circuit with outer lea

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With separate tie bar element or plural tie bars

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Details

257666, 257667, H01L 2348

Patent

active

054731895

ABSTRACT:
A lead frame for a semiconductor integrated circuit has a chip mounting section for carrying a semiconductor chip and a peripheral section where a plurality of outer leads are juxtaposed with each other. The semiconductor chip will be sealed by a sealing resin when mounted on said chip mounting section. The outer leads extend outwardly from the chip mounting section and are adapted to electrically connected with the semiconductor ship mounted. Each outer lead has a first offset portion which is spaced more from a first adjacent outer lead on one side thereof than from a second adjacent outer lead on the other side thereof and a second offset portion which is spaced more from the second adjacent outer lead than from the first adjacent outer lead. The first and second offset portions of each outer lead is arranged in a staggered pattern. Dam bars are interposed between the adjacent outer leads in a manner connecting each outer lead with the first adjacent outer lead at the first offset portion and with the second adjacent outer lead at the second offset portion for damming off the sealing resin that flows over the chip mounting section when the semiconductor chip is sealed.

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