Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2002-12-18
2004-06-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S666000, C257S667000
Reexamination Certificate
active
06756660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to lead frames for semiconductor devices and to a semiconductor device incorporating such a lead frame.
2. Background Art
There has been a trend in recent years to minimize the size of semiconductor devices. This makes possible the compact and lightweight construction of electronic appliances, and the like, incorporating the semiconductor devices. As examples of appliances, for which size and weight are key design considerations, are portable telephones, PDA devices, as well as myriad other portable electronic appliances used in many diverse environments and for different purposes. Various designs of semiconductor devices have evolved over the years to achieve the ends of miniaturization, thickness reduction and weight reduction. These devices are commonly referred to as TBGA that use a lead frame and TAB (tape automated bonding) tape, BGA (Ball Grid Array), and CSP (chip size package) that use flexible printed circuit boards. Options include wafer-scale CSP, which is the same size as the chip, and CSP, which is somewhat larger than the chip.
Of these devices, particular interest has been paid to semiconductor devices of the type wherein leads are exposed at a flat face within the confines of a resin sealed package, rather than on the edges thereof. Exemplary packages are those referred to as SON (small outline non-leaded package) and QFN (quad flat non-leaded package). Conventional lead frames of this type are shown in
FIGS. 11-18
herein.
More specifically, as shown in
FIGS. 11 and 12
, it is known to form a generally rectangular lead
10
and, through a half-etching process, form an undercut
12
through one surface
14
thereof. The undercut
12
defines a receptacle
16
for an encapsulating, sealing material, which is molded around the lead
10
in a manner so as to leave the surface
14
exposed through the sealing material. By causing the sealing material to migrate into the receptacle
16
, the tendency of the lead
10
to separate from the encapsulating, sealing material is diminished.
While the undercut
12
facilitates bonding of the encapsulating material to the lead
10
, the undercut
12
also weakens the lead
10
so as to cause a condition shown in
FIG. 12
, resulting from the electrical connection of a conductive element/wire
17
to the lead
10
. Under the force induced by a tool
18
used in electrically connecting the conductive element/wire
17
to the lead
10
, the thinned lead end
19
may bend at a line
20
coinciding with the edge of the undercut
12
so that the requisite pressure to establish the connection cannot be applied. This may cause load problems and degradation of ultrasound transfer efficiency. The inherent flexibility of the thinned lead end
19
may make stabilization of the lead end
19
during processing difficult or impossible.
To overcome this problem, it is known to stabilize the thinned lead end
19
during the electrical connection process. As seen in
FIG. 13
, a heat block
22
bears on one side
23
of a lead frame sheet
24
from which the lead
10
and a support
25
, upon which a semiconductor chip
26
is mounted, are formed. To avoid the deformation as shown in
FIG. 12
, the heat block
22
is provided with an adapter
27
which nests supportingly under the lead undercut
12
.
The use of the adapters has drawbacks. First of all, modifying the heat blocks may have to be done in many different manners to accommodate different configurations of leads. Thus, it may not be possible to develop a universal heat block form.
Additionally, with batch mold type lead frames (MAP: Mold Array Package), it may not be possible to place adapters on the heat blocks. As a result, there may be defects in the bonding of the conductive elements/wires to the leads. This problem may be further aggravated by the application of a tape conventionally used to prevent leakage of the sealing resin material during the molding process.
In
FIGS. 14 and 15
, a lead
10
′, similar to the lead
10
in
FIGS. 11 and 12
, is shown with an undercut
12
′, produced by a half-etching process, so as to reduce the thickness T of the lead end
30
from the starting thickness T1 at the opposite lead end
32
.
In
FIGS. 16-18
, a conventional half-etching process is depicted to sequentially form undercut/thinned leads
10
,
10
′ from a starting lead frame sheet
36
. Resist elements
38
are strategically placed on one side
40
of the lead frame sheet
36
to shield the region over which the leads
10
,
10
′ are to be formed. The opposite side
42
of the lead frame sheet
36
has strategically located resist elements
44
placed thereon so as to leave the region of the lead frame sheet
36
underlying the resist elements
38
exposed. With the lead frame sheet
36
and resist elements
38
,
44
in the
FIG. 16
relationship, etching is undertaken so as to progressively wear away the lead frame sheet
36
, thereby to form grooves
46
at the one side
40
of the lead frame sheet
36
between the resist elements
38
, and a single groove
48
on the opposite side
42
of the lead frame sheet
36
between the resist elements
44
. Etching continues from the
FIG. 17
state until the grooves
46
,
48
become contiguous, thereby producing the leads
10
,
10
′, which may have the same, or similar, construction to the formed leads
10
,
10
′, in
FIGS. 11
,
12
and
14
,
15
, respectively.
SUMMARY OF THE INVENTION
In one form, the invention is directed to a lead frame for a semiconductor device. The lead frame has opposite first and second sides bounded respectively by first and second parallel reference planes between which a thickness is defined. The lead frame has a support with a surface at the first side of the lead frame for receiving a semiconductor chip. A plurality of leads are spaced from the support to be electrically connected to a semiconductor chip on the support. A first lead in the plurality of leads has a length between first and second ends and a width taken transversely to the length. The first end of the first lead has a first region that has a thickness less than the thickness of the first lead at the second end of the first lead so that at least a part of the first region is offset from the second reference plane toward the first reference plane. The first end of the first lead has at least a first protrusion projecting away from the first reference plane.
In one form, the protrusion has a width less than the width of the first lead and the first end of the first lead is closer to the support than is the second lead end.
The protrusion may project towards but not fully to the second reference plane.
In one form, the protrusion tapers to an apex.
The apex may be substantially a point with the first lead viewed in cross section taken transversely to the length of the first lead.
In one form, the first lead has spaced first and second edges between which the width of the first lead is defined and the protrusion is substantially centered between the first and second edges.
In one form, the protrusion has a lengthwise extent along the length of the first lead over substantially the entire first region.
The protrusion may be centered between the first and second edges over the entire lengthwise extent of the protrusion.
In one form, the protrusion tapers to a linear apex.
The first lead may have a second protrusion projecting away from the first reference plane at a location spaced lengthwise of the first lead from the first protrusion.
The second protrusion may have a width less than the first lead.
The second protrusion may taper to an apex.
The region of the first lead may be formed by an etching process.
The invention contemplates the above lead frame in combination with a semiconductor chip mounted on the surface of the support.
The invention further contemplates a semiconductor device, consisting of the above-described lead frame with a semiconductor mounted to the support surface, a conductive element electrically connecti
Ishibashi Takahiro
Narimatsu Hiroaki
Yasunaga Shoshi
Mitsui High-tec Inc.
Nelms David
Nguyen Thinh T
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