Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-04-05
2001-05-01
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S670000, C257S671000, C257S672000, C257S673000, C257S676000
Reexamination Certificate
active
06225685
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to plastic packaging of integrated circuits, particularly to the design of a lead frame. The present invention is particularly applicable to plastic quad flat pack (PQFP) devices.
BACKGROUND ART
Conventional semiconductor chip or die packaging techniques comprise bonding a semiconductor chip to a die-attach pad secured by tie bars and then sealing by synthetic resin molding, whereby the resulting semiconductor device or package is formed. As the geometry of transistors continues to plunge into the deep sub-micron regime, plastic packaging of integrated circuits presents greater challenges to manufacturers. The reduction in the transistor size results in a smaller die with a reduced perimeter around its edges for securing bond pads which provide input/output connections to external circuitry. Each bond pad on the die is connected to an internal package lead for transferring electrical signals between the integrated circuit and external circuitry.
Conventional lead frame designs are attendant with various problems. As the geometric size of a die shrinks, at least three problems are exacerbated. Firstly, as the die shrinks in size, there is less perimeter around the die, resulting in tighter bond pad pitch. To accommodate this tighter bond pad pitch, finer diameter bond wires are conventionally used, e.g., down to about 0.9 mil. However, finer diameter wires tend to sweep to a greater degree than thickner wires during molding, thereby generating greater shorts. Secondly, there are manufacturing limits to the minimum lead frame pitch at a given lead width. Accordingly, as the die is reduced in size, the lead fingers cannot be moved proportionately, thereby resulting in longer wires. Longer wires are more vulnerable to sweep than shorter wires, thereby increasing shorts. The phenomenon known as wire sweep occurs in packaging integrated circuit devices and is particularly acute at the corner of a die because the distance between each of the corners of a polygonal lead frame and an adjacent bonding pad on the circuit chip tends to be the longest.
Conventional approaches to minimizing wire sweep and crossing involve increasing the bond pad pitch proximate the corners of the die-attach pad. However, greater bond pad pitch proximate the corners increase the dimensions of the chip, thereby increasing manufacturing costs. Another conventional approach is to shorten the bond wires by reducing the width of a metal lead. This approach, however, compromises the overall yield of wire bonding semiconductor chips and increases lead frame manufacturing costs.
Accordingly, there exists a need for a lead frame design that minimizes or eliminates electrical shorting, particularly due to mold sweep. There exists a particular need for such a lead frame design suitable for use with a submicron integrated circuit die.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a lead frame design that eliminates or substantially reduces wire sweep and wire crossing, i.e., short circuiting.
Additional advantages and other features of the present invention will be set forth in part in the description that follows and in part will become apparent to those having ordinary skill in the art upon examination of the following disclosure or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a lead frame for an integrated circuit, the lead frame comprising: a die-attach pad for supporting a semiconductor die thereon; a plurality of lead pins with inner ends arranged in an array to define a central region surrounding the die-attach pad; and a plurality of tie bars for supporting the die-attach pad, the tie bars extending from the die-attach pad between lead pins to form a gap between a tie bar and a lead pin; wherein the gap is no greater than about 18 mils.
Embodiments of the present invention comprise a substantially polygonal shaped die-attach pad having four corners and a tie bar extending from each corner. Embodiments of the present invention also comprise controlling the gap between each tie bar and a lead pin to no greater than about 15 mils, such as less than about 10 mils. Embodiments of the present invention also comprise a lead frame wherein the inner ends of the lead pins are arranged in a substantially planar array to define a substantially circular central region surrounding the dieattach pad.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein the embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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Lee Chu-Chung Stephen
Lee Melissa Siow-Lui
Newman Robert
Abraham Fetsum
Advanced Micro Devices , Inc.
Sefer Ahmed N.
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