Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-02-29
2003-03-25
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S667000
Reexamination Certificate
active
06538303
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a lead frame used for a package including a heatsink, that is used for a device such as a mold-type high-frequency power device, and a semiconductor device using the lead frame.
BACKGROUND OF THE INVENTION
A conventional semiconductor device being provided with a package including a heatsink is disclosed in, for example, in Japanese Published Unexamined Patent Application No. 130782/1995 (Tokukaihei 7-130782, published on May 19, 1995). Referring to FIGS.
6
(
a
) through
9
(
b
), the following explanation describes the construction thereof.
FIG.
6
(
a
) is a plan view showing a conventional semiconductor device in a forming process. FIG.
6
(
b
) is a sectional view taken along line
6
b
—
6
b
shown in FIG.
6
(
a
). Further, FIG.
7
(
a
) is a sectional view taken along line
7
a
—
7
a
shown in FIG.
6
(
a
). FIG.
7
(
b
) is a sectional view taken along line
7
b
—
7
b
shown in FIG.
6
(
a
). The semiconductor device (conventional example 1) is formed by a chip
52
and a package
54
including the chip
52
.
The package
54
is constituted by a lead frame
56
, bonding wires
58
, a heatsink
60
, and a sealing member
62
. The lead frame
56
is constituted by a die pad
56
a
and leads
56
b
and is provided with a chip
52
which is die-bonded via an Ag paste
64
on the die pad
56
a
. As the chip
52
, for example, a GaAsMMIC (Monolithic Microwave Integrated Circuit) chip can be adopted.
The bonding wires
58
is formed by an Au wire and has two kinds of wires of GND wires
58
a
and lead wires
58
b
for connecting chip pads
52
a
, which are formed on the chip
52
, and the die pad
56
a
or the leads
56
b
, which are formed on the lead frame
56
. A GND wiring on a circuit of the chip
52
is formed by the GND wires
58
a
, and a GND inductance occurs during an operation.
A heatsink
60
is a copper block that is entirely bonded to a back of a surface of the die pad
56
a
via a conductive paste
66
, the surface having the chip
52
disposed thereon. Further, a surface of the heatsink
60
, that is entirely bonded to the die pad
56
a
, has a back surface exposed from a sealing member
62
. When the present semiconductor device is packaged, the exposed surface is soldered onto a packaged surface. With this arrangement, it is easier to release heat occurring during an operation of the chip
52
, through the heatsink
60
to the outside of a semiconductor package.
The semiconductor device is formed in the following manufacturing process. Firstly, the copper heatsink
60
of 2.0×2.8×0.7 mm, that is separately formed, is entirely bonded via the conductive paste
66
on the back of the copper lead frame
56
having a thickness of 0.15 mm. The Ag paste
64
is applied onto the die pad
56
a
of the lead frame
56
, and the chip
52
is die-bonded.
Afterwards, by the bonding wires
58
, the chip pads
52
a
of the chip
52
are wire-bonded to the die pad
56
a
or the leads
56
b
of the lead frame
56
. And then, the semiconductor device is transfer molded by the sealing member
62
.
Next, FIGS.
8
(
a
) through
9
(
b
) show a conventional semiconductor device (conventional example 2) being provided with another conventional package including a heatsink. FIG.
8
(
a
) is a plan view showing the semiconductor device of the conventional example 2 in a forming process. FIG.
8
(
b
) is a sectional view taken along line
8
b
—
8
b
shown in FIG.
8
(
a
). And FIG.
9
(
a
) is a sectional view taken along line
9
a
—
9
a
shown in FIG.
8
(
a
). FIG.
9
(
b
) is a sectional view taken along line
9
b
—
9
b
shown in FIG.
8
(
a
). Here, those members that have the same functions and that are described in conventional example 1 are indicated by the same reference numerals and the description thereof is omitted.
Here, conventional example 2 is different from conventional example 1 as follows: in conventional example 2, a lead frame
56
of a semiconductor device does not include a die pad
56
a
(see FIG.
6
(
a
)), and a heatsink
60
also serves as a die pad. Further, in the lead frame
56
, lower surfaces of all leads
56
b
are mounted on the upper surface of the heatsink
60
via an insulating paste
68
. Moreover, GND wires
58
a
are bonded onto the upper surface of the heatsink
60
and form a GND wiring on a circuit of a chip
52
, so that a GND inductance occurs during an operation.
The semiconductor device of conventional example 2 is formed in the following manufacturing process. Firstly, a Ag paste
64
is applied to the center of the surface of the heatsink
60
that has the chip
52
mounted thereon, and the chip
52
is die-bonded. And then, the heatsink
60
and the lead frame
56
are disposed with the insulating paste
68
. Afterwards, the chip pads
52
a
are wire-bonded to the leads
56
b
or the upper surface of the heatsink
60
also serving as the die pad
56
a
. And then, the semiconductor device is completed after performing the same process as conventional example 1.
Incidentally, when the semiconductor device, particularly a high-frequency power device is packaged into a resin mold, a heat-releasing property and a high-frequency property are important. Namely, in view of releasing heat, the chip
52
has a large amount of self-heating, so that it is necessary to reduce and simplify (reduce heat resistance) a heating path and to release generated heat efficiently to the outside so as to restrict a higher temperature in the chip
52
. Moreover, in view of the high-frequency property, a GND inductance needs to be minimized.
However, a package
54
used for a semiconductor device of the conventional art has the following problem regarding a heat-releasing path and a GND inductance.
Firstly, in conventional example 1, on the heat-releasing path, many members are disposed between the chip
52
serving as a heat-releasing part and the outside of the semiconductor device. The heat-releasing path has an extremely large heat resistance of, for example, 50° C./W.
FIG. 10
shows the heat-releasing path under such a condition for each heat resistance (simple resistance).
FIG. 10
is a conceptual drawing showing the heat-releasing path of conventional example 1. To be specific, the heat-releasing path is: a heat-releasing part of the chip
52
→a base member of the chip
52
(R
1
)→the Ag paste
64
(R
2
)→die pad
56
a
(R
3
)→a conductive paste
66
(R
4
)→the heatsink
60
(R
5
)→the outside of the package
54
. This can be cumulatively expressed as follows: package heat resistance: Rth=R
1
+R
2
+R
3
+R
4
+R
5
.
As described above, conventional example 1 has a long and complicated heat-releasing path, so that the package heat resistance is high. Thus, when the semiconductor device of conventional example 1 is continuously operated, the temperature may rise too much inside the package
54
. When the temperature is too high in the package
54
, the following phenomenon appears so as to cause a problem. Firstly, an output power value serving as an electrical property is reduced with time. Further, even when an input power is increased to obtain a desired output power, the output power value is at saturation due to a high temperature of the inside, so that the output power value cannot be raised any more.
In order to solve the problem, it is necessary to shorten and simplify the heat-releasing path to a minimum, to reduce heat resistance of the package
54
, and to improve a heat-releasing property so as to prevent an increase in temperature inside the package
54
. Hence, conventional example 2 achieves a construction which does not include the die pad
56
a
so as to realize a heat-releasing path in which R
3
and R
4
are omitted.
Here, in conventional example 2, the lead frame
56
and the heatsink
60
are mounted on the leads
56
b
of the lead frame
56
. The leads
56
b
are separated later to form terminals of the semiconductor device, so that the leads
56
b
need to be electrically insulated. Therefore, a part for mounting
Meier Stephen D.
Nixon & Vanderhye PC
Rose Kusha
Sharp Kabushiki Kaisha
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