Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-08-29
2002-10-15
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S112000
Reexamination Certificate
active
06465279
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a lead frame and a production method thereof, and a semiconductor device using the lead frame and a fabrication method thereof.
Referring to
FIG. 4
, there is shown one related art semiconductor device using a lead frame generally designated by character “a”. The lead frame “a” has a number of leads “b”, and a die pad “c” on which a semiconductor element “d” is bonded by means of an adhesive “e”. It should be noted that the die pad “c” is depressed for making the thickness of the semiconductor device as thin as possible. Respective electrodes of the semiconductor element “d” are connected to the corresponding leads “b” via bonding wires “f”. The semiconductor element “d” thus mounted is then sealed with a sealing resin “g”.
Referring to
FIG. 5
, there is shown another related art semiconductor device using a lead frame generally designated by character “a”. In this example, to mount a plurality of semiconductor elements “d”, the lead frame “a” includes a printed circuit board “h” having an interconnection film for connecting the plurality of semiconductor elements “d” to each other. To be more specific, the printed circuit board “h” is bonded on a die pad “c” of the lead frame “a” by means of an adhesive “e”, the plurality of semiconductor elements “d” are mounted on the printed circuit board “h”, electrodes of the semiconductor elements “d” are connected to the interconnection film on the printed circuit board “h” via bonding wires “f”, and the interconnection film on the printed circuit bard “h” is connected to leads “b” via bonding wires “f”.
In the case of mounting the plurality of semiconductor elements “d”, it is required to provide a number of interconnections for connecting the semiconductor elements “d” to each other. For the semiconductor device shown in
FIG. 5
, such interconnections are configured as interconnection portions obtained by patterning the interconnection film on the printed circuit board “h”.
The related art semiconductor device shown in
FIG. 4
, however, has a problem that it cannot incorporate a plurality of semiconductor elements “d” because the lead frame “a” has no function as interconnections for connecting the plurality of semiconductor elements “d” to each other.
In recent years, along with strong demands toward multiple functions, higher degree of integration, and miniaturization of semiconductor devices, it has been required to incorporate a plurality of semiconductor elements (LSI chips) in one semiconductor device. From this viewpoint, the semiconductor device shown in
FIG. 4
, which cannot meet such a requirement, should be regarded as being poor in usability.
On the contrary, the semiconductor device shown in
FIG. 5
can mount a plurality of semiconductor elements “d” by connecting them to each other via the printed circuit board “h”, and therefore, it can meet the above-described demands toward multiple functions and higher degree of integration, and the like. In this regard, the semiconductor device shown in
FIG. 5
is superior to the semiconductor device shown in FIG.
4
.
The semiconductor device shown in
FIG. 5
, however, has problems caused by use of the printed circuit board “h”. The first problem lies in that since the printed circuit board “h” is additionally provided, the thickness of the semiconductor device is correspondingly increased. For a semiconductor device particularly required to be thinly designed, even a slight increase in thickness equivalent to the thickness of a printed circuit board may be often non-negligible.
The second problem lies in that a positional deviation inevitably occurs between the printed circuit board “h” and the lead frame “a” upon connection therebetween, with a result that it is difficult to ensure a necessary accuracy in positioning the printed circuit board “h” to the lead frame “a”.
The third problem lies in that since the production process requires the additional step of connecting the bonding wires “f” made from gold or the like to the interconnection film on the printed circuit board “h” by means of expensive means such as brazing, the production cost is raised, for example. Although the technique of bonding the wires “f” made from gold or the like to the lead frame “a” has been already established, the technique of connecting the wires “f” to the printed circuit board “h” by means of die bonding or wire bonding has been little performed, and therefore, has been not established yet. As a result, if the technique of connecting the wires “f” to the printed circuit board “h” is carried out, there occur inconveniences associated with degradation in yield, reliability, and cost. That is to say, the process of producing the semiconductor device shown in
FIG. 5
by using the technique of connecting the wires “f” to the printed circuit board “h” is poor in practical utility.
Additionally, it may be considered to use a TAB tape in place of the printed circuit board “h”; however, in this case, since the TAB tape must be connected to the lead frame, there arise problems that the same positional deviation as described above occurs, and that the connection of the TAB tape to the lead frame is complicated, and since the connection is performed at a high temperature, the TAB tape may be deformed due to a residual stress caused by heat generated upon high temperature connection, with a result that it is very difficult to stably connect the TAB tape to the lead frame. Accordingly, like the process of producing the semiconductor device using the printed circuit board, the process of producing the semiconductor device using the TBA tape is poor in practical utility.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a lead frame having interconnection means capable of electrically connecting a plurality of semiconductor elements mounted on the lead frame, thereby mounting the plurality of semiconductor elements on one semiconductor device, and to provide a semiconductor device using the lead frame, which device can desirably mount a plurality of semiconductor elements while thinning the thickness of the semiconductor device, and which can be produced without increasing the number of assembling steps and degrading the reliability and yield.
To achieve the above object, according to a first aspect of the present invention, there is provided a lead frame including: outer leads formed by a metal base member; first interconnection film portions formed by a metal plating layer, each of which is disposed inside the outer leads in such a manner as to be connected to an inner end of one principal plane of the corresponding one of the outer leads, and at least one second interconnection film portion formed by the metal plating layer, which is disposed inside the outer leads in such a manner as not to be connected to the outer leads; and an insulating film formed to cover planes, opposed to the outer leads, of the first and second interconnection film portions, thereby holding the first and second interconnection film portions; wherein planes, opposed to the insulating film, of the first and second interconnection film portions are taken as semiconductor element mounting planes.
With this configuration, since the lead frame has the first and second interconnection film portions, semiconductor elements mounted on the lead frame can be electrically connected to each other via the second interconnection film portion not connected to the outer leads. Since the second interconnection film portion not connected to the outer leads is held by the insulating film, it can be kept in its position although being separated from the outer leads. Accordingly, a plurality of semiconductor elements can be mounted on the lead frame. Further, since the interconnection film portions are formed, inside the outer leads formed by the metal base member, on one surface side of the outer leads, and the planes, on the outer lead side, of the interconnection film portions are taken as the semiconductor mounting planes, the thickness of the portion, on w
Kusano Hidetoshi
Ohsawa Kenji
Sonnenschein Nath & Rosenthal
Talbott David L.
Zarneke David A.
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