LDO regulator having an adaptive zero frequency circuit

Details LDO regulator having an adaptive zero frequency circuit LDO regulator having an adaptive zero frequency circuit

2001-04-11

2003-08-05

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S274000

Reexamination Certificate

active

06603292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to low dropout voltage regulators. More particularly, the present invention relates to the field of frequency compensation schemes for low dropout voltage regulators.
2. Related Art
The phenomenal growth in portable, battery-operated devices has fueled the growth of the low dropout voltage (LDO) regulator market. The LDO regulator is characterized by its low dropout voltage. Dropout voltage is the difference between the input voltage (unregulated voltage received from an unregulated source, such a battery or a transformer) to the LDO regulator and the output voltage (regulated voltage) from the LDO regulator. Typically, the output voltage of the LDO regulator drops out of regulation if the dropout voltage is not maintained. The low dropout voltage of the LDO regulator extends the life of the battery since the LDO regulator provides a regulated voltage even if the battery is discharged to a value that is within (typically) 100-500 millivolts of the regulated voltage. The LDO regulator is incorporated into portable devices such as cellular phones, cordless phones, pagers, personal digital assistants, portable personal computers, camcorders, digital cameras, etc.
FIG. 1
illustrates a conventional LDO regulator
100
according to the prior art. As illustrated in
FIG. 1
, the conventional LDO regulator
100
includes a pass device
10
which provides an output current I
out
which drives the load resistance
50
coupled to the output
30
of the conventional LDO regulator
100
. The conventional LDO regulator
100
receives the unregulated voltage V
in
and provides the regulated voltage V
out
at its output
30
. Typically, a capacitor C
output
(the load capacitor) is coupled to the output
30
of the conventional LDO regulator
100
to improve the transient response of the conventional LDO regulator
100
. Moreover, the manufacturer of the capacitor C
output
models the parasitic elements inside the capacitor C
output
by assigning an Equivalent Series Resistance (ESR) to the capacitor C
output
, whereas the ESR is positioned in series with the capacitor C
output
.
To obtain a low dropout voltage, the pass device
10
is implemented as a PNP transistor coupled in the common-emitter configuration. Additionally, a low dropout voltage can be obtained if the pass device
10
is implemented as a p-type channel MOSFET (PMOS) coupled in the common-source configuration.
The PMOS (or the PNP transistor) implemented as the pass device
10
adds an additional low-frequency pole in the transfer function which provides the frequency response of the conventional LDO regulator
100
. Moreover, the frequency of this low-frequency pole is dependent on both the value of the load resistance
50
and the value of the capacitor C
output
. The load resistance
50
varies widely from application to application and even within a particular application. Hence, the low-frequency pole has a variable frequency. The presence of the low-frequency pole (having the variable frequency) requires the utilization of a dominant pole compensation scheme as well as an additional compensation scheme. Typically, the additional compensation is achieved by introducing a well-defined zero. This well-defined zero is provided by the capacitor C
output
and the ESR of the capacitor C
output
.
Typically, the manufacturer of the conventional LDO regulator
100
specifies for each value of the capacitor C
output
, a minimum value and a maximum value for the ESR to ensure the stability of the conventional LDO regulator
100
under a range of load resistances
50
. Often, the manufacturer specifies an expensive and bulky capacitor C
output
to target a precise combination of capacitance and ESR. Typically, electrolytic capacitors and tantalum capacitors are bulky and expensive compared to ceramic capacitors. Moreover, electrolytic capacitors and tantalum capacitors have an ESR which can be several Ohms while ceramic capacitors have an ESR which is typically between several milliohms and several hundred milliohms. The goal is to achieve a capacitor C
output
whose ESR is neither too high nor too low to maintain the stability of the conventional LDO regulator
100
and to keep it from oscillating.
Typically, the required ESR value for a specified value of the capacitor C
output
ranges from hundred(s) of milliohms to several Ohms. Although ceramic capacitors are preferred because of their limited space requirements and cost advantages, this range of values for the ESR generally prohibits the use of ceramic capacitors for the capacitor C
output
, unless an additional resistor is added in series with the capacitor C
output
.
SUMMARY OF THE INVENTION
A low dropout voltage (LDO) regulator having an adaptive zero frequency circuit is described. The adaptive zero frequency circuit maintains the stability of the LDO regulator and improves the transient response of the LDO regulator under a range of values for the output current, whereas the output current inversely varies with the load resistance coupled to the output of the LDO regulator. The adaptive zero frequency circuit generates a zero having a frequency which varies with the output current. Hence, the frequency of the zero changes to maintain the stability of the LDO regulator despite the variation in the frequency of the low-frequency pole generated by the load resistance and the load capacitance (or output capacitor) coupled to the output of the LDO regulator.
Moreover, the Equivalent Series Resistance (ESR) of the output capacitor is no longer critical for maintaining the stability of the LDO regulator. Therefore, a broad range of capacitor types can be implemented as the output capacitor, including a ceramic capacitor. The ceramic capacitor requires a minimal amount of space on a printed circuit board and is significantly less expensive than other capacitor types, such as an electrolytic capacitor or a tantalum capacitor. Moreover, the ceramic capacitor has a small ESR compared to the ESR of an electrolytic capacitor or a tantalum capacitor. The transient response of the LDO regulator is improved by using an output capacitor having a small ESR.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
In one embodiment, the present invention includes a frequency compensation circuit for a low dropout voltage (LDO) regulator having an amplifying stage and a pass device stage, comprising: a current sensing circuit coupled to the pass device stage, the current sensing circuit generating a sense current that varies with an output current generated by the pass device stage; and an adaptive zero frequency (AZF) circuit coupled to the current sensing circuit, coupled to a ground terminal of the LDO regulator, and coupled to an output terminal of the amplifying stage, wherein the AZF circuit generates a zero in a frequency response of the LDO regulator, and wherein the zero has a frequency which varies with the sense current so that to maintain stability in the LDO regulator and to improve transient response of the LDO regulator under a range of values for the output current.
In another embodiment, the present invention includes a low dropout voltage (LDO) regulator comprising: an error amplifier having an amplifying stage and a pass device stage, the error amplifier generating a regulated voltage at an output of the LDO regulator; a current sensing circuit coupled to the pass device stage, the current sensing circuit generating a sense current that varies with an output current generated by the pass device stage at the output of the LDO regulator; and an adaptive zero frequency (AZF) circuit coupled to the current sensing circuit, coupled to a ground terminal of the LDO regulator, and coupled to an output terminal of the amplifying stage, wherein the AZF circuit generates a zero in a frequency response

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