LDD transistor process having doping sensitive endpoint etching

Fishing – trapping – and vermin destroying

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437 27, 437 34, 437 41, 437 57, 437191, 437233, 437 29, 437 30, 357 233, 357 59, 156643, 156646, 156650, 156653, H01L 21265, H01L 2128, H01L 27092

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049786261

ABSTRACT:
An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

REFERENCES:
patent: 4249968 (1981-02-01), Gardiner et al.
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 4358338 (1982-11-01), Downey et al.
patent: 4377436 (1983-03-01), Donnelly et al.
patent: 4602981 (1986-07-01), Chen et al.
patent: 4675072 (1987-06-01), Bennett et al.
patent: 4714519 (1987-12-01), Pfiester
patent: 4717446 (1988-01-01), Nagy et al.
patent: 4757026 (1988-07-01), Woo et al.
patent: 4818715 (1989-04-01), Chao
patent: 4829024 (1989-05-01), Klein et al.
patent: 4837180 (1989-06-01), Chao
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4863879 (1989-09-01), Kwok
patent: 4888298 (1989-12-01), Rivaud et al.
patent: 4906589 (1990-03-01), Chao
patent: 4908326 (1990-03-01), Ma et al.
Huang et al., "A Novel Submicron LLD Transistor with Inverse-T Gate Structure", IEDM, 12/1986, pp. 742-745.
"Simultaneous Formation of Shallow-Deep Stepped Source/Drain For Sub-Micron CMOS", by C. S. Oh et al., 1988, Symposium on VLSI Technology/Digest of Techical Papers, pp. 73-74, May 10-13, 1988.
"A Novel Submicron LDD Transistor With Inverse-T Gate Structure", by Tiao-Yuan Huang et al., 1986 IEEE International Electron Devices Meeting Technical Digest, pp. 742-745, Dec. 7-10, 1986.
"The Impact of Gate-Drain Overlapped LDD (Gold) For Deep Submicron VLSI's", by Tyuichi Izawa et al., 1987 IEEE International Electron Device Meeting Technical Digest, pp. 38-41, Dec. 6-9, 1987.

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