Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-11-03
2002-03-12
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S192000
Reexamination Certificate
active
06356320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (“LCD”) apparatus and a method of manufacturing thereof, and more specifically, to a method of manufacturing and structure of an LCD apparatus which eliminates stitching defects caused by an irregularity in a width of a gate line or data line.
2. Description of the Background Art
In general, a liquid crystal display device includes a TFT array substrate. In the structure of the TFT array substrate as shown in
FIGS. 1 and 2
, a plurality of gate bus lines
60
are arranged horizontally and are spaced from each other by a certain distance. A plurality of data bus lines
70
are arranged vertically and are spaced from each other by a certain distance. The gate bus lines
60
and the data bus lines
70
are arranged so that the data bus lines
70
and the gate bus lines
60
intersect each other so as to define a matrix array.
A gate pad
60
a
and a data pad
70
a
which are in contact with a drive IC are defined at the end of the gate bus line
60
and the data bus line
70
. A pixel electrode
40
is defined in each block area defined by the intersections of the gate bus line
60
and the data bus line
70
and a TFT
50
is also defined at the intersection point of the gate bus line
60
and the data bus line
70
.
The TFT
50
includes a gate electrode
60
b
which is made from material used to form the gate bus line
60
, a source electrode
70
b
and a drain electrode
70
c
which are made from a material used to form the data bus line
70
, and a semiconductor layer
90
. The drain electrode
70
c
of the TFT is in contact with the pixel electrode
40
.
A display device that is manufactured by simultaneously defining a gate bus line and a data bus line is suitable when forming a large LCD with the above-mentioned structure, which has more than a 14 or 15 inch display area. However, due to technical limitations in manufacturing such a display device, the size of an area that can be exposed at one time is limited. For example, for large panels, a one-shot exposing process cannot be used since the panel is too large for conventional exposing equipment.
Therefore, in order to expose a large substrate, a divided exposure method is used. In the divided exposure method, a first portion of a substrate is exposed first and then a second, remaining part of the substrate is exposed. However, using the divided exposure method results in a difference in line width at a boundary line between the first area exposed by the first exposing step and the second area exposed by the second exposure step. Note that this difference in line width causes a difference in the resistance in the lines, which causes differences in luminance in the display. This luminance difference is called a stitching defect.
As shown in
FIG. 3
a
, a metal layer
55
in which a desired pattern is to be defined is disposed on a transparent substrate
10
using the divided exposure method. In order to perform the divided exposure method on a large substrate
11
which is covered with a photo resist layer
80
, the area of the photo resist layer is divided into part A and part B. An exposure mask
100
, which exposes part A of the photo resist layer
80
and a border line D that divides parts A and B are located in the same position. The exposure mask
100
includes an exposure pattern
150
which is used to patter part A of the photo resist layer [of part A] of the substrate
11
into a certain pattern and a light blocking member
140
. A light such as a UV ray which radiates from an exposure device on the exposure mask
100
penetrates the exposure pattern
150
and exposes the photo resist of part A of the substrate
11
with a certain pattern.
Then, an exposure mask
200
is located to be aligned with the border line D in order to expose part B of the photo resist layer
80
after eliminating the prior exposure mask
100
as shown in
FIG. 3
b
. The exposure mask
200
includes an exposure pattern
151
and a light blocking member
141
in order to exposure part B of the photo resist layer
80
of the substrate
11
. A light such as a UV ray which radiates from an exposure device on the exposure mask
200
penetrates the exposure pattern
151
and exposes the photo resist of part B of the substrate
11
with a certain pattern so at the end parts A and B which are divided by the border line D of the exposure mask are exposed into a certain pattern.
After exposing the photo resist into a certain pattern using each exposure mask
100
and
200
, the photo resist layer
80
is developed and while using the developed photo resist pattern layer as a mask, a lower metal layer
55
is etched to define a data bus line
70
and a drain electrode
70
c
having a structure as shown in
FIG. 4. A
width (a) of a line such as the data bus line
70
, which is located at the border part D of the divided exposure, is formed differently from widths (b) and (c) of the data bus lines
70
that are directly adjacent to the dividing line D as shown in
FIGS. 4 and 5
. The reason for the difference in the width pattern of the line formed at the border part of the divided exposure is because a metal layer is etched along the pattern of the photo resist. In other words, when resetting and attempting to locate the exposure mask
200
at an identical position after partly exposing the photo resist with the exposure mask
100
, the rest of the photo resist is exposed in a state in which the location of the pattern of the exposure mask is slightly out of place or misaligned due to an error in positioning of the mask and the metal layer is etched according to such a pattern of the photo resist.
The patterned width (a) of the data bus line
70
at the border part D of the divided exposure is wider than the widths (b) and (c) of the data bus lines
70
which are directly adjacent to the dividing line D if the exposure mask
200
is placed to the right of line D as shown in FIG.
4
. On the other hand, the patterned width (a) of the data bus line
70
at the border part D of the divided exposure is narrower than the widths (b) and (c) of the data bus lines
70
that are directly adjacent to the dividing line D if the exposure mask
200
is placed to the left of line D as shown in FIG.
5
.
The substrate
11
of an LCD apparatus includes the pixel electrode
40
in contact with the drain electrode
70
c
. The TFT is formed such that the data bus line
70
is formed in the above described manner. When the screen of an LCD apparatus including each one of the pixel electrodes
40
is checked by applying power to the data pad
70
a
at an end of the data bus line
70
and the gate pad
60
a
at an end of the gate bus line
60
, the problem of the stitching defect is determined at the border part D of the divided exposure.
The stitching defect is identified by a difference in the resistance value of each line and this difference in resistance is due to the fact that the width (a) of the data bus line
70
at the border part D of the divided exposure is different from the widths (b) and (c) of the data bus lines
70
that are directly adjacent to the dividing line D. Therefore, when using the divided exposure method for making a large substrate, the occurrence of the stitching defect still cannot be avoided even though there is some improvement in the degree of occurrence compared to suing an exposure method which exposes a substrate using a one-shot exposure process.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention overcome the problems of the conventional art described above by correcting the stitching defect which occurs at the border area of the divided exposure when the gate bus line and the data bus line are patterned using conventional divided exposure methods.
In a preferred embodiment of the present invention, a liquid crystal display includes a substrate, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed on the substrate and arranged to define a matrix pattern wit
Choo Kyo Seop
Chung In Jae
LG. Philips LCD Co. Ltd.
Schechter Andrew
Ton Toan
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