LCD testing method

Details LCD testing method LCD testing method

2001-08-27

2004-04-13

Cuneo, Kamand (Department: 2878)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

C324S073100, C324S1540PB

Reexamination Certificate

active

06720791

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an LCD testing method. In particular, the present invention relates to an LCD testing method reducing the testing time and increasing yield.
2. Description of the Related Art
New technologies have made thin-film-transistor liquid-crystal-display (TFT LCD) units with higher resolution and larger panel size highly accessible. TFT-LCDs with resolution higher than 1224×768 and panels larger than 14 inches (such as XGA and SXGA specifications) have become standard for notebook computers. As technology advances, quality control has become a crucial concern. The quality of the LCD is largely concerned with pixel output, affected by broken circuits, current leakage of the TFT and parasitic capacitance.
A typical testing method to assess the likelihood of these problems occurring is the charge-coupled-device (CCD) captured image match method. First, the panel is lit by an optical system. The pixel image on the panel is then captured with the CCD and transformed to digital signals that are then analyzed. Defective pixels are thus detected.
Another testing method frequently used is to connect an array tester to the signal lines and gate lines on a substrate of a TFT-LCD. The array tester sequentially transmits predetermined signals to the signal lines or gate lines, then sequentially receives and analyzes the signals fed back by the signal lines or gate lines to locate the defective pixels. Array testers such as the IBM array tester use probe tips to contact the outer pin of each signal or gate line and transmit the predetermined signals to the signal or gate lines. The signals fed back from the signal or gate lines are then analyzed as IV curves using components such as integrators. If any IV curve does not match the predetermined standard, the existence of defective pixels is determined, and subsequently identified using an apparatus such as an electronic microscope.
FIG. 1
shows the signal lines in an LCD array. Notation
100
represents the overall LCD signal lines in a manufacturing process. Each signal line comprises a first end
1
, a second end
2
and a periphery bonding pad
3
. The first end
1
and the second end
2
respectively have electro-static-discharge (BSD) protection devices to protect the LCD from ESD events. The second end
2
is usually trimmed off after the manufacturing process is completed. The array tester is connected to the pad
3
to carry out the test against the LCD array pixels together with cooperation of the gate lines (not shown).
Some limits exist, however, to the testing method described above. The pin
10
process technology is one concern. Using an LCD in XGA specification as an example, there are 768 gate lines, and 3072 (=1024×3) signal lines (each pixel unit is comprised of the 3 pixel dots of R, G and B). To carry out the test, the probe tips must precisely contact the outer pin of the gate lines and the signal lines (the PAD). When the resolution increases, the accuracy of the pins and the apparatus rectifying the probe tips touching the outer pins must increase. Furthermore, the higher pixel count in larger LCDs also requires more time to be tested. For example, an LCD in the above specification contains 2359296 pixels (3072×768) which will take a considerable amount of time to test. Testing times have a major effect on manufacturing costs. With good quality control, if the testing time is efficiently reduced, the yield will improve considerably. When LCD manufacturing technology has achieved a certain yield rate, the chance of any two non-defective pixels on the panel occurring is considerable. Therefore, the testing method should not be limited to the conventional one-by-one mode. The conventional method neglects the ability of the array testers to test two pixels at any given time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an LCD testing method. The method comprises forming jump lines in a predetermined region on the substrate between the signal lines via mask design when forming TFT LCD arrays, thus forming a plurality of signal-line groups, each with two signal lines coupled by the jump lines. Thereupon, an array tester sequentially tests two pixels corresponding to the signal lines in the signal groups. When a feedback signal from the signal groups does not meet a predetermined standard, it is determined that one or both pixels in the signal group are defective. The defective pixel or pixels are then identified using an optical apparatus such as an electronic microscope. The optical apparatus has a scope covering two pixel units to test two pixels at the same time. Therefore, the numbers of the probe pins and the tests carry carried out is halved. The probe pin size is thus less restrictive due to larger probe pin intervals. Consequently, the yield is greatly increased. After the manufacturing process, the predetermined region is trimmed off to re-establish the separation of the signal lines.
More specifically, the present invention provides an LCD panel testing method for testing a plurality of pixel units in an LCD panel having a plurality of corresponding gate lines and n signal lines Pi~P
n
. The method comprises: providing a substrate; providing an LCD panel on the substrate, having the signal lines Pi~P
n
sequentially arranged on one side of the LCD panel; dividing the signal lines Pi~P
n
to form a plurality of signal-line groups, each signal-line group comprising at least two of the signal lines; providing a sacrifice area on the substrate to couple the signal lines in the signal-line groups; and providing a testing device having a plurality of first probe tips and a plurality of second probe tips, wherein the first probe tips are respectively coupled to the gate lines, and the second probe tips are respectively coupled to the signal-line groups so that the testing device sequentially tests the pixel units corresponding to one of the gate lines and one of the signal-line groups. After the testing device has finished testing all the pixel units, the sacrifice area is trimmed off from the substrate with a trimmer to re-establish the separation of the signal lines. If any of the signal lines are not assigned to the signal-line groups, the pixel units on the unassigned signal lines are sequentially tested with one of the first probe tips and one of the second probe tips.
The method of dividing the signal lines P
l
~P
n
into a plurality of signal-line groups can be any of the following: (1) putting the signal lines P
6i+j
and P
6i+j+3
into a signal-line group, wherein i and j are integers, and 0≦i≦n/6, 1≦j≦3. (2)
1. putting the signal lines P
2i+1
and P
2i+2
into a signal-line group, wherein i is an integer, and 0≦i≦n/6, 1≦j≦3. Or (3) putting the signal lines P
4i+j
and P
4i+j+2
into a signal-line group, wherein i and j are integers, and 0≦i≦n/4, 1≦j≦2. The testing device comprises an LCD array tester, electronic microscope, CCD captured image matching system or other conventional instruments.


REFERENCES:
patent: 5657139 (1997-08-01), Hayashi
patent: 6437596 (2002-08-01), Jenkins et al.

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