LCD panel and LCD device equipped therewith

Details LCD panel and LCD device equipped therewith LCD panel and LCD device equipped therewith

2000-03-03

2003-07-01

Saras, Steven (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S087000

Reexamination Certificate

active

06587089

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Liquid-Crystal Display (LCD) panel having a pair of transparent substrates and a Liquid-Crystal (LC) layer. sandwiched between the pair of substrates, in which driving elements such as Thin-Film Transistors (TFTs) and Metal-Insulator-Metal (MIM) elements are arranged regularly on one of the pair of substrates, and an LCD device formed by using the panel. More particularly, the present invention relates to an LCD panel and an LCD device of the active-matrix addressing type that are applicable to compact, light-weight display devices with a comparative wide display area and that are capable of displaying images in different modes or aspects of resolution, which are typically used for electronic equipment, such as various portable or non-portable display terminals.
2. Description of the Prior Art
FIGS. 1 and 2
schematically show the configuration and operation of a prior-art LCD device of this sort, respectively.
The prior-art LCD device of
FIG. 1
has a TFT panel
120
including a plurality of LC cells
105
arranged in a matrix array having m rows and U columns, a drain driver
107
for driving the panel
120
, and a gaze driver
108
for driving the same, where m and n are positive integers greater than unity. The first to m-th rows of the matrix extend along the X axis in FIG.
1
and arranged along the Y direction in
FIG. 1
at equal intervals. The first to n-th columns of the matrix extend along the Y axis and arranged along the X direction at equal intervals.
A TFT
102
is formed in each of the plurality of LC cells
105
. Each cell
105
serves as a capacitor along with a display electrode (not shown) and a common electrode (not shown). Thus, the cell
105
is illustrated in
FIG. 1
by a symbol of a capacitor. Each cell
105
corresponds to a pixel of the LCD device.
While the display electrodes are formed on the inner surface of a transparent glass substrate
101
along with the TFTs
102
, the common electrodes are formed on the inner surface of another transparent glass substrate (not shown) that is coupled with the substrate
101
to be opposed thereto. Needless to say, a LC layer is formed in the space between the substrate
101
and the opposing substrate.
On the inner surface of the substrate
101
, first to m-th gate lines
128
-
1
,
128
-
2
, . . . , and
128
-m, first to n-th drain lines
127
-
1
,
127
-
2
, . . . , and
127
-n, and the TFTs
102
are formed. The m gate lines
128
-
1
to
128
-m extend respectively along the m rows of the matrix. The n drain lines
127
-
1
to
127
-n extend respectively along the n columns of the matrix. The TFPTs
102
are located at the respective intersections of the gate lines
128
-
1
to
128
-m and the drain lines
127
-
1
to
127
-n. Thus, the total number of the TFTs
102
is equal to (m×n).
The gate lines
128
-
1
to
128
-m, which are parallel to each other, are electrically connected to the gate driver
108
located outside the substrate
101
. The drain lines
127
-
1
to
127
-n, which are parallel to each other and perpendicular to the gate lines
128
-
1
to
128
-m, are electrically connected to the drain driver
107
located outside the substrate
101
.
Each of the n drain lines
127
-
1
to
127
-n is electrically connected to the drain electrodes D of the TFTs
102
that are aligned along the corresponding drain line
127
-
1
,
127
-
2
, . . . , or
127
-n (i.e., the corresponding column of the matrix). Each of the m gate lines
128
-
1
to
128
-m is electrically connected to the gate electrodes G of the TFTs
102
that are aligned along the corresponding gate line
128
-
1
,
128
-
2
, . . . , or
128
-m (i.e., the corresponding row of the matrix).
The source S of each of the TFTs
102
is electrically connected to one of the two electrodes forming the corresponding LC cell
105
(i.e., the corresponding display electrode) formed on the substrate
101
. The other electrodes of the cells
105
(i.e., the common electrode) are electrically connected to a common voltage source, such as the ground.
The gate driver
108
is applied with a vertical start signal VSP
0
and a vertically-shifting clock signal VCK
0
. In response to the signals VSP
0
and VCK
0
, the gate driver
108
generates selection signals VG
1
, VG
2
, . . . , and VGm to select a corresponding one of the rows of the matrix and then, supplies them to the corresponding gate lines
128
-
1
,
128
-
2
, . . . , and
128
-m, respectively.
The drain driver
107
is applied with an image signal DAT
0
, a horizontal start signal HSP
0
, a horizontally-shifting clock signal HCK
0
, and a latch signal LP
0
. In response to the signals DAT
0
, HSP
0
, HCK
0
, and LP
0
, the drain driver
107
generates pixel data signals HD
1
, HD
2
, . . . , and HDn to form images and then, supplies them to the corresponding drain lines
127
-
1
to
127
-n, respectively The supply or input of the pixel data signals HD
1
to HDn is controlled by the latch signal LP
0
.
The prior-art LCD device shown in
FIG. 1
operates in the following way.
The application of the horizontal start signal HSP
0
to the drain driver
107
triggers off the input of the image signal DAT
0
for one of the m rows of the matrix into the driver
10
?. The input of the image signal DAT
0
is performed to be synchronized with the application of the horizontally-shifting clock signal HCK
0
. Based on the applied image signal DAT
0
, the drain driver
107
generates the pixel data signals HD
1
to HDn for one of the m rows of the matrix and then, supplies them simultaneously to the drain lines
127
-
1
to
127
-n with specific timing, respectively.
On the other hand, the application of the vertical start signal VSP
0
to the gate driver
108
triggers off the generation of the selection signals VG
1
to VGm. Then, the driver
108
sequentially supplies the selection signals VG
1
to VGm to the gate lines
128
-
1
to
128
-m, respectively. As shown in
FIG. 2
, each of the signals VG
1
to VGm contains a pulse and therefore, the TFTs
102
applied with the signal VG
1
, VG
2
, . . . , or VGm at their gate electrodes are turned on. Through the TFTs
102
thus turned on, the drain lines
127
-
1
to
127
-n are electrically connected to the corresponding LCD cells
105
, thereby selecting the cells
105
arranged along one of the m rows of the matrix. Since the pulses of the signals VG
1
to VGm are successively shifted in phase to each other, the cells
105
arranged along each of the first to m-th rows of the matrix are successively selected.
The pixel data signals HD
1
to HDn are respectively supplied to the selected cells
105
located in the selected rows of the matrix and then, the pixel data contained in the signals HD
1
to HDn are written thereinto. Thus, the cells
105
are driven by the signals HD
1
to HDn, thereby displaying images on the screen of the prior-art LCD device corresponding to the pixel data thus written.
Typically, the selection signals VG
1
to VGm have waveforms A
1
to Am denoted by the solid lines in
FIG. 2
at the input ends
128
-
1
A to
128
-mA of the gate lines
128
-
1
to
128
-m, respectively. On the other hand, the signals VG
1
to VGm have waveforms B
1
to Bm denoted by the broken lines in
FIG. 2
at the output ends
128
-
1
B to
128
-mB of the lines
128
-
1
to
128
-m, respectively. It is seen from
FIG. 2
that each of the waveforms Bl to Bm includes obtuse rising and falling edges at the output ends
128
-
1
B to
128
-mB. The obtuse rising and falling edges of the waveforms Bl to Bm will cause some temporal shift in or phase delay &Dgr;t
0
of the waveforms Al to Am The shift or delay &Dgr;t
0
has been known as the “gate line delay”, which is induced by the resistance of the lines
128
-
1
to
128
-m and parasitic capacitances existing near the lines
128
-
1
to
128
-m.
Accordingly, the supply timing of the pixel data signals HD
1
to HDn needs to be properly adjusted while taking the “gate line delay” &Dgr;t
0
into consideration.

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