Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2001-06-26
2003-04-15
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C257S059000, C349S046000
Reexamination Certificate
active
06549251
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2000-40005, filed Jul. 12, 2000 in Korea, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active-matrix liquid crystal display (LCD) device and a method of fabricating the same, and more particularly, to an array substrate having thin film transistors (TFTs) for the active-matrix LCD device and the method of fabricating the array substrate.
2. Discussion of the Related Art
A LCD device makes use of optical anisotropy to display images. A typical LCD device includes an upper substrate, a lower substrate, and a liquid crystal material interposed therebetween.
FIG. 1
is an exploded perspective view showing a typical LCD device
11
including an upper substrate
5
and an opposing lower substrate
22
and a liquid crystal layer
14
interposed therebetween. The upper substrate
5
and the lower substrates
22
are alternatively called a color filter substrate and an array substrate, respectively. On the upper substrate
5
, a black matrix
6
and a color filter layer
7
that includes a plurality of sub-color-filters red (R), green (G), and blue (B) are formed. The black matrix
6
surrounds each sub-color-filter, thereby forming an array matrix. Further on the upper substrate
5
, a common electrode
18
is formed to cover the color filter layer
7
and the black matrix
6
.
On the lower substrate
22
opposing the upper substrate
5
, a thin film transistor (TFT) “T” is formed to function a switching element in the shape of an array matrix corresponding to the color filter layer
7
. In addition, a plurality of crossing gate lines
13
and data lines
15
are positioned such that the TFT “T” is located proximate to each crossing portion of the gate line
13
and the data line
15
. The crossing gate line
15
and the data line
15
define a pixel region “P”. In the pixel region “P”, a pixel electrode
17
is disposed and is made of a transparent conductive material, usually indium tin oxide (ITO), for example.
Liquid crystal molecules of the liquid crystal layer
14
are aligned in accordance with electric signals applied by the TFT “T”, thereby controlling transmission of incident rays of light to form a display image. Specifically, the gate line
13
and the data line
15
apply electric signals to a gate electrode and a source electrode of the TFT “T,” respectively. The signal applied to the drain electrode is transmitted to the pixel electrode
17
in order to align the liquid crystal molecules of the liquid crystal layer
14
. Subsequently, rays of backlight (not shown) selectively pass through the liquid crystal layer
14
such that an image is displayed. A fabricating process of the array substrate requires repeated steps of deposition, photolithography, etching, and stripping for various layers.
In practice, an inverted staggered type TFT is widely deployed due to its simplicity and high quality and can be classified as either a back-channel-etch type or an etching-stopper type, based on the method of forming a channel. The etch-stopper type TFT is alternatively referred to as a channel-passivated type, because it further includes a channel passivation layer that protects the channel of the TFT. More processes are required for fabricating the etch-stopper type TFT because of the channel passivation layer. However, the channel passivation layer effectively decreases passage of electrons across the channel, thereby improving operational quality. In addition, because the channel passivation layer protects the channel from being over-etched during fabrication, generation of defects within the channel is prevented.
FIG. 2
shows an array substrate of a liquid crystal display device implementing a conventional inverted staggered type TFT. As shown, the array substrate
22
includes a pixel region “P” defined by crossing gate line
13
and data line
15
, and includes a TFT “T”, a pixel electrode
17
, and a storage capacitor “C.” The TFT “T” includes a gate electrode
26
, a source electrode
28
, a drain electrode
30
, and an active layer
55
. An island-shaped channel passivation layer
57
is disposed upon the active layer
55
, and is made of an insulating material. The source electrode
28
electrically connects with the data line
15
, the gate electrode
26
electrically connects with the gate line
13
, and the pixel electrode
17
directly contacts the drain electrode
30
.
Referring now to
FIGS. 3A
to
6
A and
3
B to
6
B, a method for fabricating the conventional array substrate will now be explained.
FIGS. 3A
to
6
A are sequential plan views showing the array substrate during the fabrication process, and
FIGS. 3B
to
6
B are cross-sectional views taken along a line “III—III” of FIG.
2
.
FIGS. 3B
to
6
B correspond to
FIGS. 3A
to
6
A, respectively.
In
FIGS. 3A and 3B
, a surface of a substrate
22
is cleaned to remove particles and/or contaminants. Then, a first metal layer is deposited upon the substrate
22
using a sputtering process, for example, and is subsequently patterned using a first mask to integrally form a gate electrode
26
and a gate line
13
. At this point, a portion of the gate line
13
is used as a first capacitor electrode
13
a
of the storage capacitor “C” shown in FIG.
2
. Aluminum (Al) is widely used as the material with which to form the gate electrode
26
for decreasing RC delay. However, pure aluminum is chemically weak and may result in the formation of hillocks during high-temperature processing. Accordingly, instead of pure aluminum, aluminum alloys or layered aluminum structures are used to form the gate electrode. As mentioned above, the gate electrode
26
and the first capacitor electrode
13
a
are usually made of the same metal layer as the gate line
13
. After the first metal layer is patterned, a gate insulating layer
50
is formed to cover the first metal layer. Then, an amorphous silicon layer (a-Si:H)
55
and an insulating layer
57
are sequentially formed upon the gate insulating layer
50
.
In
FIGS. 4A and 4B
, the insulating layer
57
is patterned to form an island-shaped channel passivation layer
57
a
disposed over the gate electrode
26
. Then, a doped amorphous silicon is deposited upon the channel passivation layer
57
a
and the amorphous silicon layer
55
(in FIG.
3
B). The doped amorphous silicon layer and the amorphous silicon layer are patterned together to form an island-shaped ohmic contact layer
58
and an active layer
55
a
with the channel passivation layer
57
a
interposed therebetween.
Thereafter, as shown in
FIGS. 5A and 5B
, a second metal layer is deposited upon the array substrate
22
and subsequently patterned to form a data line
15
, a source electrode
28
, and a drain electrode
30
. The data line
15
crosses with the gate line
13
to define a pixel region “P.” The source electrode
28
and the drain electrode
30
are spaced apart from each other and formed to overlap the gate electrode
26
with the active layer
55
a
interposed therebetween.
As shown in
FIGS. 6A and 6B
, a transparent conductive material is deposited upon the array substrate
22
and subsequently patterned to form a pixel electrode
17
disposed in the pixel region “P.” The transparent conductive material is preferably selected from a group including at least indium tin oxide (ITO) and indium zinc oxide (IZO), for example. The pixel electrode
17
electrically contacts the drain electrode
30
at a drain edge portion “D” and a portion of the pixel electrode
17
overlaps the first capacitor electrode
13
a
and functions as a second capacitor electrode
17
a
. The first capacitor electrode
13
a
and the second capacitor electrode
17
a
compose the storage capacitor “C.” Thereafter, a passivation layer
60
is formed to cover an entire surface of the array substrate
22
having the pixel electrode
17
.
During the above fabrication processes, the pixel electrode
17
is usually patterned using a wet etching method. However, when an etc
LG.Philips LCD Co. , Ltd.
Ton Toan
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