Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-08-21
2004-04-27
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06727879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an LCD driver used in a multi-line selection driving method (called “MLS method” thereafter) for simultaneously driving a plurality of rows of a super twisted nematic liquid crystal display (STN-LCD). The LCD comprises a plurality of pixels that are arranged in a matrix, where one pixel of color data includes a plurality of bits.
2. Description of Related Art
An LCD driver in the MLS method simultaneously drives a plurality of rows (common) of the STN-LCD at a predetermined potential. The LCD driver in the MLS method drives each column (segment) at a plurality of potentials. For example, a potential is selected from among one plus the number of simultaneously driven rows in accordance with color data in order to achieve a rapid response display.
An outline of the structure of an LCD driver in the conventional MLS method and problems thereof will be described below with reference to
FIGS. 5
to
7
.
FIG. 5
is an outline view of an example of the LCD driver in the conventional MLS method.
An LCD driver
30
includes a line counter
32
, a line decoder
34
, and a display memory
36
. The LCD driver
30
drives four rows of an LCD simultaneously. Further, the LCD driver
30
includes line registers
37
, a scrambler
38
, EXOR gates
40
, an adder
42
, a potential selection register
43
, and a potential selector
44
for each column corresponding to each RGB (Red, Green, Blue) color.
In the exemplified LCD driver
30
, clock signals are counted by the line counter
32
, and the counter value of the line counter
32
is decoded by the line decoder
34
. One word signal W[4m+n] corresponding to the counter value is sequentially activated for every count. When the word signal is activated, color data stored in one word in the display memory
36
corresponding to the activated word signal is output.
In the display memory
36
shown in
FIG. 5
, one horizontal row represents color data for one word. Each set of color data for the word in the display memory
36
corresponds to a color (gray scale) of each column for one row of the LCD. Color data for one pixel is represented by gray scale data of three colors stored in the display memory
36
as a unit of RGB. For example, R(4m+0,0), G(4m+0,0), and B(4m+0,0) at the upper left in the display memory represents RGB color data for one pixel at the 0th row and 0th column among four rows simultaneously driven of the LCD.
Further, for example, R(4m+0,0), R(4m+1,0), R(4m+2,0) and R(4m+3,0) represents each R data at the 0th column for the four simultaneously driven rows of the LCD. Furthermore, R(4m+0, 1), R(4m+1,1), R(4m+2, 1) and R(4m+3, 1) represent each R data at the first column of the four simultaneously driven rows of the LCD. It should be noted that this method also applies to the G and B data.
The color data for one pixel includes 8 bits of display memory in the case of 256 color (gray scale) display as shown, for example, in FIG.
6
. This example is arranged such that, in one pixel of color data, 3 bits (7 to 5) at the most significant bit (MSB) side are data for R, the following 3 bits (4 to 2) are data for G, and the 2 bits (1 and 0) at the least significant bit (LSB) side are data for B. In this case, each of R and G produces an 8-gray scale display and B produces a 4-gray scale display, resulting in a total of 256 color (gray scales) display. Writing to or reading from the display memory
36
using an external controller (not shown) is performed for color data by a row decoder and a column decoder (not shown).
Color data for four simultaneously driven rows of the LCD are sequentially output from the display memory
36
in synchronization with a clock signal CLK, as shown in a timing chart in FIG.
7
. Here, the color data output from the display memory, for example, within the 0th column of data R(0-3, 0), data R(0,0) at the 0th row and 0th column of R, data R(1,0) at the first row and 0th column of R, and data R(2,0) at the second row and 0th column of R, are held in positions 0, 1, and 2 of the line registers
37
at the rising edges of the clock signals CLK
0
,
1
, and
2
, respectively.
In the LCD driver
30
, as shown in the example, because color data for the 0th to third rows are output from the display memory
36
sequentially by timesharing, data R(0-2, 0) at the 0th to second rows and 0th column of R are held in the line registers
37
once. Data R(0-2, 0) at the 0th to second and 0th column of R held in the line registers
37
are input to corresponding scramblers
38
, respectively. On the other hand, data R(3,0) at the third row and 0th column of R is not held in the line register
37
, but is input to the corresponding scrambler
38
directly.
The example shown adopts a frame-rate-control (FRC) method as a modulation method for gray scale display. In this case, the gray scale display is implemented by selecting, in accordance with gray scale data stored in the display memory
36
, a ratio of the number of frames to be turned on or off by each pixel within the predetermined number of frames (pattern), and by controlling the ratio by timesharing. Gray scale conversion data of R is time-sequential data prepared for each gray scale corresponding to each gray scale of R and indicating the ratio for being turned on or off for each pixel. For example, gray scale conversion data of R is selected according to the gray scale represented by the data R (0-3, 0) at 0th column of R, and gray scale display of the corresponding pixel is performed based on the data.
In the example shown, in accordance with data R(0-3,0) at the 0th column of R and gray scale conversion data of R, signals corresponding to the gray scales represented by the data R(0-3,0) at the 0th column of R are output from the respective scramblers
38
. The signals output from the scramblers
38
undergoes an exclusive-OR operation with corresponding row electrode selection patterns 0 to 3 by the EXOR gate
40
, respectively. Then, each operation's result is added by the adder
42
, and held in a potential selection register
43
in synchronization with a clock signal CLK
3
.
The row electrode selection patterns 0 to 3 represent column components that have an orthogonal relation with the row direction to each other in a row selection matrix provided for the LCD driver
30
. An example of the row selection matrix is shown in FIG.
8
. The column components of the row selection matrix correspond to the four simultaneously driven rows of the LCD. In the LCD driver
30
used in the MLS method, the exclusive-OR operation between color data at each column of each simultaneously driven row of the LCD and corresponding column components in the row selection matrix is executed. Then, a potential corresponding to the arithmetic addition is selected in order to drive each column of the LCD.
The signal output from the adder
42
is input to the potential selection register
43
. Then, one potential out of several potentials is selected and output by the potential selector
44
. The number of the several potentials is equal to the number of simultaneously driven rows of the LCD plus one. For example, in this case, one potential out of five potentials (V
0
to V
4
) is selected. The 0th column of R in the LCD is driven at the potential output from the potential selector
44
. It should be noted that each column of each color in the LCD is driven similarly at the corresponding potential output from potential selector
44
.
In the LCD driver used in the conventional MLS method, color data for one row is sequentially output by the row from the display memory
36
. Thus, in order to drive four rows simultaneously, color data for at least three out of the four rows driven is required to be held in the line register
37
in advance. Therefore, like a mobile phone, if one pixel of color data includes 8 bits and an STN-LCD has 128 columns of pixel for one row, line registers are required for 128 columns×8 bits×3
JFE Steel Corporation
Liang Regina
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