LCD driver for layout and power savings

Details LCD driver for layout and power savings LCD driver for layout and power savings

2000-12-19

2003-11-25

Shalwala, Bipin (Department: 2673)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S204000, C345S690000, C345S692000, C365S230060, C326S107000, C341S152000, C341S153000

Reexamination Certificate

active

06653998

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to liquid crystal display (LCD) drivers, and more particularly, to digital signal control circuits and methods for conserving power and minimizing layout space for use with LCD drivers.
2. Background Art
LCD displays are commonly used for applications such as computer display monitors, television monitors, and other devices for displaying text, photo, video, or other types of information. LCD displays may be made of certain types of liquid crystal display material, as is well understood by those familiar with display technologies. In typical LCDs, liquid crystal material fills the space or gap between a pair of row and column substrates to form a cell or pixel. Perpendicular row and column electrodes are patterned on to the respective substrates to permit an electric potential to be selectively created at particular points (i.e., cells) on the display to alter the appearance of the liquid crystal material. Row and column (data) drivers are utilized to address selected cells.
Each of these LCD (row and column) drivers receive an n-bit digital input data that is used to select one out of 2
n
voltage levels to be provided to the desired row or column electrodes.
FIG. 1
illustrates a conventional LCD driver circuit where n is equal to 2. The 2-bit input data is processed by a 2×4 decoder for selecting one of the four digital lines {D
00
, D
01
, D
10
, D
11
} to pass one of the four voltage levels {V
0
, V
1
, V
2
, V
3
} to an output circuit and then on to the desired electrode. An optional sample and hold circuit designated S&H is provided at the output for boosting the signal strength of the output analog voltage.
FIG. 2
illustrates a known signal-line routing scheme based on the conventional LCD driver in FIG.
1
. The four voltage lines carrying the voltage levels {V
0
, V
1
, V
2
, V
3
} are M
2
(metal-
2
) lines, and the four decoded lines for carrying the decoded digital signals are M
1
(metal-
1
) lines. The M
2
and M
1
lines are arranged perpendicular to each other. The output is used for driving one column of the LCD cells. The M
2
lines that carry the analog voltages {V
0
, V
1
, V
2
, V
3
} extend further from what is illustrated in
FIG. 2
, and are used to drive other columns of LCD cells via other decoders.
FIG. 3
illustrates the LCD driver circuit and routing scheme that is similar to a commercial LCD driver distributed by NEC Corp., and known as the “NEC uPD16632”. For simplicity, only n=2 bits are shown in
FIG. 3
to select one of four voltage levels for output driving. There are 2n (i.e., 4) digital signal lines {a, a-bar, b, b-bar} that are used for controlling a matrix of 2n×2
n
(i.e., 16) pass transistors, for selecting one of 2
n
(i.e., 4) voltage levels as the output voltage. As compared with
FIGS. 1 and 2
, no decoder is used to process the digital input data. The voltage levels {V
0
, V
1
, V
2
, V
3
} are carried by metal lines that are fabricated by a metal-
1
or metal-
2
layer. The 2
n
digital signal lines are carried by polysilicon lines that are perpendicular to the metal lines. Due to the column pitch and metal/polysilicon line pitch considerations, even though the number of pass transistors {M
00
, M
01
, . . . , M
33
} used is significantly higher than illustrated in
FIGS. 1 and 2
, the actual layout is not necessarily larger, and can actually be smaller, than the layout in
FIGS. 1 and 2
.
The pass transistors in
FIG. 3
that have been circled (i.e., M
00
, M
02
, M
10
, M
13
, M
21
, M
22
, M
31
, M
33
} are depletion implanted to a negative threshold voltage so that they are always turned “ON” regardless of the voltage level (i.e., high or low) of each digital signal line {a, a-bar, b, b-bar}. In other words, these depletion implanted transistors operate as “don't care” transistors that pass whatever voltages are transmitted therethrough. The negative threshold voltage of these depletion implanted pass transistors enables the use of polysilicon lines as both the digital signal lines and the gates of those pass transistors to achieve savings in layout. This will become apparent by viewing the layout shown in FIG.
4
.
FIG. 4
is a top view of a layout that is similar to the layout of the NEC uPD16632 of FIG.
3
. In this example, n=3 bits are used. As a result, there are 2n (i.e., 6) digital signal lines {a, a-bar, b, b-bar, c, c-bar}, and 2
n
(i.e., 8) voltage levels {V
0
, V
1
, V
2
, V
3
, V
4
, V
5
, V
6
, V
7
}. These eight voltage levels are carried by eight active regions labeled AR that include diffusion regions (e.g., n+ implanted). As known in the art, a diffusion region is an n+ or p+ implanted and later diffused region (due to thermal cycles) in an active region surrounded by field oxide isolation. These eight voltage levels {V
0
, V
1
, V
2
, V
3
, V
4
, V
5
, V
6
, V
7
} are divided into even-numbered voltage levels {V
0
, V
2
, V
4
, V
6
} at one side of the layout of
FIG. 4
, and odd-numbered voltage levels {V
1
, V
3
, V
5
, V
7
} at another side of the layout of
FIG. 4. A
DAC output node is coupled to the action regions AR through metal-
1
lines and metal-to-diffusion contacts. The six digital signal lines {a, a-bar, b, b-bar, c, c-bar} are carried by polysilicon lines, with six digital signal lines {a, a-bar, b, b-bar, c, c-bar} on a different side of the layout. A pass transistor PT is formed where each polysilicon line {a, a-bar, b, b-bar, c, c-bar} crosses an active region AR, with the portion of the polysilicon overlapping the active region AR as the gate for the pass transistor. Again, each circled pass transistor is depletion implanted through the use of a mask.
As shown in
FIG. 4
, the voltage levels {V
0
, V
1
, V
2
, V
3
, V
4
, V
5
, V
6
, V
7
} increase monotonously from V
0
through V
7
. For example, V
0
will be selected as the output voltage if {a}, {b} and {c} are all digital “low” (i.e., 0). This is because the {a}, {b} and {c} lines overlap depletion implanted transistors at the voltage level for V
0
(i.e., the voltage V
0
passes through), and the {a-bar}, {b-bar} and {c-bar} lines will carry a “high” signal (i.e., a=0, b=0, c=0) to pass the voltage level V
0
to the DAC output. As a further example, V
1
will be selected as the output voltage if {a} and {b} are all digital “low” (i.e., 0), and {c} is digital “high”. This is because the {a}, {b} and {c-bar} lines overlap depletion implanted transistors at the voltage level for V
1
(i.e., the voltage V
1
passes through), and the {a-bar}, {b-bar} and {c} lines will carry a “high” signal (i.e., a=0, b=0, c
32
1) to pass the voltage level V
1
to the DAC output. As yet another example, V
6
will be selected as the output voltage if {c} is digital “low” (i.e., 0), and {a} and {b} are both digital “high”. This is because the {a-bar}, {b-bar} and {c} lines overlap depletion implanted transistors at the voltage level for V
6
(i.e., the voltage V
6
passes through), and the {a}, {b} and {c-bar} lines will carry a “high” signal (i.e., a=1, b=1, c=0) to pass the voltage level V
6
to the DAC output. Using the same methodology, and given the layout illustrated in
FIG. 4
, the corresponding digital signals and selected voltage levels are as follows:
a
b
c
Voltage Level Selected
0
0
0
V0
0
0
1
V1
0
1
0
V2
0
1
1
V3
1
0
0
V4
1
0
1
V5
1
1
0
V6
1
1
1
V7
Unfortunately, the layouts in
FIGS. 3 and 4
suffer from the drawbacks that they take up much space, and require a large amount of power for driving the circuit.

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