LC tank clock driver with automatic tuning

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Reexamination Certificate

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Details

C327S299000

Reexamination Certificate

active

07126403

ABSTRACT:
A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.

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patent: 6650163 (2003-11-01), Burns et al.
“A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology,” Lee et al.,IEEE J. of Solid-State Circuits,vol. 38, n. 12 (Dec. 2003).
“A Two-Chip 1.5-GBd Serial Link Interface,” Walker et al.,IEEE J. of Solid-State Circuits,vol. 27, n. 12 (Dec. 1992).
“A Plastic Packaged 10 Gb/s BiCMOS Clock and Data Recovering 1:4-Demultiplexer with External VCO,” Hauenschild et al.,IEEE J. of Solid-State Circuits,vol. 31, n. 12 (Dec. 1996).
“An 800mW 10Gb Ethernet Transceiver in 0.13μm CMOS,” Sidiropoulos et al.,IEEE International Slid-State Circuits Conference,session 9 (2004).

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