Layout techniques for memory circuitry

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S052000

Reexamination Certificate

active

07324364

ABSTRACT:
An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of VSSplanes are interconnected with the switching devices. The switching devices and the VSSplanes are formed at a first level. The VSSplanes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.

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Dudeck et al., “Decoding Techniques for Read-Only Memory,” U.S. Appl. No. 11/363,366, filed Feb. 27, 2006.

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