Layout technique for semiconductor processing using stitching

Details Layout technique for semiconductor processing using stitching Layout technique for semiconductor processing using stitching

2000-10-12

2003-08-12

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S129000, C257S448000, C250S492220

Reexamination Certificate

active

06605488

ABSTRACT:

BACKGROUND
The present disclosure generally relates to image sensors, and more specifically, to layout techniques for image sensor components using stitching.
Many semiconductor-processing foundries have a maximum lithographic size that they may use to form a chip. A common limit, for example, is 20×20 mm
2
. Making a chip larger than that maximum size may be carried out using stitching. Stitching forms different portions of the chip in different areas of the wafer. The different areas are then “stitched” together to form the overall chip.
Complicated chips may require a large number of stitches to form an entire circuit. The complexity of the chips may mean higher cost, lower throughput, and higher risk to produce the chip. For example,
FIG. 1
shows a layout of a prior art system for the 2K×2K sensor
100
. In the illustrated example, the sensor needs a total of 17 blocks on the reticle and needs to be stitched 24 times.
SUMMARY
The present system teaches a technique and structure for simplifying the stitching process. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout technique for row/column decoder that reduces the number of blocks when stitching.


REFERENCES:
patent: 5652163 (1997-07-01), Schinella et al.
patent: 6137535 (2000-10-01), Meyers
patent: 6225013 (2001-05-01), Cohen et al.
Kirihata et al., “A 220-mm2, Four- and Eight-Bank, 256-Mb SDRAM with Single-Sided Stitched WL Architecture”, IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, pp. 1711-1719.

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