Layout structures of data input/output pads and peripheral...

Details Layout structures of data input/output pads and peripheral... Layout structures of data input/output pads and peripheral...

2005-01-25

2005-01-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000

Reexamination Certificate

active

06847576

ABSTRACT:
Integrated circuit memory devices include a first memory block. The first memory block includes first and second memory array banks and a first peripheral circuit. The first peripheral circuit is disposed between the first and second memory array banks such that a length of a first data path from the first memory array bank to the first peripheral circuit is about equal to a length of a second data path from the second memory array bank to the first peripheral circuit.

REFERENCES:
patent: 5072280 (1991-12-01), Matsukura
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5771200 (1998-06-01), Cho et al.
patent: 5812490 (1998-09-01), Tsukude
patent: 6498714 (2002-12-01), Fujisawa et al.
patent: 1999-40435 (1999-06-01), None

Affiliated with

Also associated with

Rating

Layout structures of data input/output pads and peripheral... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout structures of data input/output pads and peripheral..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout structures of data input/output pads and peripheral... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3405925