Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-07-20
2010-02-09
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S203000, C365S205000
Reexamination Certificate
active
07660141
ABSTRACT:
Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of a bit line and a complementary bit line may be arranged in the first region. First, second and third equalization MOS transistors of an equalizer that equalizes the bit line and the complementary bit line may be arranged In the second region located apart from the first region, Sensing NMOS transistors and equalization NMOS transistors may share an N-type active region in the layout structure of a memory device, and the area of a sense amplifier may be reduced.
REFERENCES:
patent: 6262922 (2001-07-01), Nakamura et al.
patent: 6721221 (2004-04-01), Schreck
patent: 7138684 (2006-11-01), Hidaka et al.
patent: 7184330 (2007-02-01), Tajima et al.
patent: 06-140592 (1994-05-01), None
patent: 2004-0041097 (2004-05-01), None
Office Action for corresponding Korean Application No. 10-2006-096132 dated Aug. 31, 2007.
Harness Dickey & Pierce PLC
Ho Hoai V
Samsung Electronics Co,. Ltd
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