Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-07-12
2004-09-21
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S700000
Reexamination Certificate
active
06794744
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention generally relates to a layout structure and method, more particularly, to a layout structure and method for supporting central processing units having two different package techniques.
1. Description of Related Art
The Pentium IV central processing unit (abbreviated as CPU) developed by Intel Corporation has two different package types: one type of CPU has 423 pins and uses the pin grid array (abbreviated as PGA) package; the other type of CPU has 478 pins and uses the ball grid array (abbreviated as BGA) package. Since these two different package techniques are configured on a motherboard that has 6 layers and 4 layers stack structure respectively, it needs to use a layout structure of different printed circuit boards and has to cooperate with different north bridge control chips to work properly. Therefore, it is not only inconvenient in usage, but also the manufacture cost is increased.
The conventional stack structure of the printed circuit board of the 423 pins Pentium IV CPU is shown in Table 1:
TABLE 1
Top Signal Layer
Grounded Layer
Inner Signal Layer
Grounded Layer
Power Layer
Bottom Solder Layer
From Table 1, the printed circuit board uses a 6 layers stack structure. From up to down, the stack structure sequentially comprises a top signal layer, a grounded layer, an inner signal layer, a grounded layer, a power layer, and a bottom solder layer.
FIG. 1
schematically shows a power layer cut ichnography in the area where the signals of the north bridge control chip
102
are coupled to the signals of the CPU
100
in the layout structure of a motherboard that supports the 423 pins Pentium IV CPU. From Table 1, since all the signals of the north bridge control chip
102
that are coupled to the CPU
100
are placed on the top signal layer and the grounded layer, all the signals of the north bridge control chip
102
that are coupled to the CPU
100
can refer to the grounded layer. Therefore, high quality of the signal transmission can be assured. On the other hand, from the layout structure of Table 1 and
FIG. 1
, since the power layer
104
of the north bridge control chip
102
that is coupled to the CPU
100
does not comprise a grounded potential, if the signals of the north bridge control chip
102
that are coupled to the CPU
100
are to be placed on the bottom solder layer, it has to cross over the power layer
104
to refer to the grounded area, thus the signal transmission quality is not as good as in the top signal layer. Consequently, the conventional bottom solder layer is seldom used to place the signals of the north bridge control chip that are coupled to the CPU.
On the other hand, the stack structure of the conventional printed circuit board that supports the 478 pins Pentium IV CPU is shown in Table 2:
TABLE 2
The area of the north bridge
The area of the north bridge
control chip where its
control chip where its
signals are not coupled to
signals are coupled to the
CPU (The
the CPU (The third area)
CPU (The second area)
first area)
Top Signal Layer
Top Signal Layer
Top Signal
Layer
GND
GND
GND
The Cut Layer of the
GND
GND
interface operating voltage
source
Bottom Solder Layer
Bottom Solder Layer
Bottom
Solder Layer
From Table 2, the printed circuit board uses a 4 layers stack structure, comprising: a first area, where the whole CPU is placed in the first area; a second area, all the signals of the north bridge control chip that are coupled to the CPU are placed in the second area; a third area, all the signals of the north bridge control chip that are not coupled to the CPU are placed in the third area. From Table 2, the stack structure of the first area from up to down sequentially comprises a top signal layer, a grounded layer (GND), a power layer having an interface operating voltage source (to generate a voltage source via the appropriate cutting, and each interface voltage source varies based on the difference of the connected devices), and a bottom solder layer. The stack structure of the second area and third area from up to down sequentially comprises a top signal layer, a grounded layer, a grounded layer, and a bottom solder layer. All the signals of the Intel designed north bridge control chip that are connected to the CPU are placed on the top signal layer, and all refer to the contiguous grounded layer. However, since most of the signals are placed on the top signal layer, thus the area used by the north bridge control chip is increased, and greater printed circuit board is demanded to constitute the control chip, moreover the area of the north bridge control chip that is coupled to the CPU is also increased accordingly, so that the demand of the layout length can be met. These limitations cause great concern in designing the north bridge control chip and the motherboard.
Obviously, since the stack structure of these two Intel Pentium IV CPUs mentioned above are different, the prior art has to use two different layout structures and printed circuit boards to support two different Intel Pentium IV CPUs that have different package types. As a result, Intel has been forced to develop two different types of the north bridge control chip to support the corresponding Pentium IV CPU respectively. Consequently, in order to support the Intel Pentium IV CPUs of two different package types, not only does the motherboard need to be re-laid out, but the north bridge control chip also needs to be replaced. This results in usage inconveniency and cost increase.
SUMMARY OF INVENTION
Therefore, the present invention provides a layout structure and its layout method to configure a layout structure that supports the CPUs of two different package techniques on a 4 layers structure motherboard. Furthermore, the north bridge control chip used by the present invention can support two different types of the Intel Pentium IV CPU. Therefore, the usage convenience can be improved and the cost can be saved.
In order to achieve the objective mentioned above and other objectives, the layout structure of the preferred embodiment according to the present invention from up to down sequentially comprises: a first signal layer; a first reference layer having a first reference potential; a second reference layer having a first reference area and a second reference area, the first reference area comprises a first reference potential, the second reference area comprises a second reference potential; and a second signal layer. Wherein, the layout structure is placed in the area between the CPU that and the control chip, and the first reference potential can be a grounded potential.
In the preferred embodiment of the present invention, the first reference potential in the second reference layer is placed in one side of the north bridge control chip nearest the CPU, and the second reference layer cuts into the north bridge control chip from the other side.
The present invention further provides a motherboard that supports the CPUs of two different package techniques, the motherboard is used to place the CPU and the control chip, comprising: a first area, the whole CPU is placed in the range of the first area, the stack structure of the first area from up to down sequentially comprises a first signal layer; a first reference layer having a first reference potential; a second reference layer having a first reference area and a second reference area, the first reference area comprises a first reference potential, the second reference area comprises a second reference potential; and a second signal layer. The motherboard further comprises a second area, all the signals of the control chip that are coupled to the CPU are placed in the range of the second area, the stack structure of the second area from up to down sequentially comprises a third signal layer; a third reference layer having a first reference potential; a fourth reference layer having a third reference area and a fourth reference area, the third reference area comprises a first reference potential, the fourth reference area comprises a second refere
Chang Nai-Shung
Chen Shu-Hui
Chen Tsai-Sheng
Jiang Chyun IP Office
Thai Luan
VIA Technologies Inc.
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