Fishing – trapping – and vermin destroying
Patent
1993-06-18
1994-06-21
Thomas, Tom
Fishing, trapping, and vermin destroying
437 60, 437919, H01L 2170
Patent
active
053224388
ABSTRACT:
The present invention relates to the field of capacitor layout schemes for integrated circuits. A method comprising nine specific layout criteria is disclosed that eliminates or greatly suppresses problems of prior art capacitance matching. The nine layout criteria for providing precise capacitance ratios are: 1) fixed horizontal and vertical spacings are maintained for unit capacitors; 2) grounded dummy unit capacitors are placed around the periphery of each capacitor group; 3) two interconnects are used per unit capacitor; 4) equal numbers of top and bottom external interconnects per capacitance are maintained; 5) the external interconnect capacitance is made equal to the internal interconnect capacitance; 6) nonunit capacitors are used in the largest capacitance in a ratio; 7) the top plate interconnect of a capacitance is isolated from the bottom plate interconnect of the same capacitance; 8) interconnects are shielded from opposite capacitor plates; and, 9) rows of unit capacitors of the same capacitance are isolated from each other. This layout scheme provides improved accuracy and reproducibility for capacitance matching in silicon integrated circuits. Another advantage of this method is that, by limiting the options available for laying out matched capacitor structures, the layout process is streamlined in a manner that reduces time and, in particular, lends itself to automation. Still another advantage of it is that less space is required for the same circuit in most cases.
REFERENCES:
Yaghutiel, H. et al., "Automatic Layout of Switched Capacitor Filters for Custom Applications", 1988 IEEE Int. Solid State Circuits Conference, pp. 170-171.
Hershbarger Russell
McNutt Michael
Silicon Systems Inc.
Thomas Tom
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