Layout pattern verification system

Details Layout pattern verification system Layout pattern verification system

1990-06-28

1993-04-13

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

052028410

ABSTRACT:
In the inventive layout pattern verification system, verification data employed by a verification data judging part for judging effectiveness/defectiveness of the electrical property of a logic circuit formed by a layout pattern are data calculated by a verification data calculation part on the basis of reference circuit constants extracted from layout pattern data by a second data extraction part and process parameters supplied by a process parameter supply part, i.e., data obtained with no circuit simulation. Thus, the electrical property of the layout pattern of a large-scale logic circuit can also be easily verified by judging effectiveness/defectiveness of the electrical property of the logic circuit formed by a layout pattern through a verification data judging part on the basis of the verification data.

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"Excl: A Circuit Extractor for IC Designs" by S. P. McCormick, IEEE 21st Design Automation Conf., 1984, pp. 616-623.
"LAS: Layout Pattern Analysis System with New Approach" by Y. Okamura et al., IEEE 1982, pp. 308-311.

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