Layout pattern generation device for semiconductor integrated ci

Details Layout pattern generation device for semiconductor integrated ci Layout pattern generation device for semiconductor integrated ci

1997-06-13

1999-10-26

Teska, Kevin J.

39550004, G06F 1750

Patent

active

059742445

ABSTRACT:
A layout pattern generation method and device executing this method in which a symbolic layout of a semiconductor integrated circuit is generated, the sizes of transistors are changed by using the circuit connection information of the layout pattern, the correspondence information of the transistors whose sizes have been changed are generated by using the symbolic layout and the changed circuit connection information, the symbolic layout after the transistor sizes have been changed is generated by using the correspondence information, the generated symbolic layout is compacted, and then a new layout pattern is generated by using the compacted layout pattern.

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