Layout pattern generation and geometric processing system for LS

Details Layout pattern generation and geometric processing system for LS Layout pattern generation and geometric processing system for LS

1989-03-10

1991-10-29

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

050620541

ABSTRACT:
A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.

REFERENCES:
patent: 4651284 (1987-03-01), Watanabe et al.
patent: 4791586 (1988-12-01), Maeda et al.
patent: 4829446 (1989-05-01), Draney
patent: 4835705 (1989-05-01), Fujino et al.
patent: 4837447 (1989-06-01), Pierce et al.
patent: 4858143 (1989-08-01), Fournier
"A New Cad System for Automatic Logic Interconnection Verification", Miyahara et al., Musahino Electrical Communication Lab., IEEE, pp. 114-117, 1981.

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