Layout parameter extraction device

Patent

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Details

39550019, H05K 702

Patent

active

060289910

ABSTRACT:
Circuit connection information extracting means reads circuit information. The circuit information has a hierarchical structure having an upper hierarchy including a plurality of instance cells and an interconnect for connecting the instance cells, and a lower hierarchy acting as connection information (internal nets) in the instance cells. When extracting a partial circuit, only nets belonging to the upper hierarchy are specified as net selection information. Instance cell extracting means inputs the net selection information, decides whether or not all the nets connected to the instance cells are specified by the net selection information, and extracts any instance cells in which all the nets are specified. Net name generating means recognizes the internal nets for each extracted instance cell, attaches net names capable of uniquely identifying nodes to the internal nets, and stores the net names as additional net information. Selective circuit extracting means extracts a partial circuit to which the nets belong on the basis of the net selection information and the additional net information. Accordingly, necessary sets of nets can automatically be obtained to easily select a partial circuit to be simulated only by specifying a small number of nets.

REFERENCES:
patent: 5572436 (1996-11-01), Dangelo
patent: 5631841 (1997-05-01), Kishida

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