Layout overlap detection with selective flattening in computer i

Details Layout overlap detection with selective flattening in computer i Layout overlap detection with selective flattening in computer i

1997-09-30

2000-01-04

Teska, Kevin J.

G06F 1750

Patent

active

06011911&

ABSTRACT:
The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein. Once overlap is detected, the areas of the layout data corresponding to the overlap areas are selectively flattened prior to proceeding to DRC and LVS processing. During selective flattening of the overlap areas, the hierarchical tree is traversed from the top cell down through intermediate nodes to the leaf nodes. Each time geometry data is located during the traversal, it is pushes directly to the top cell without being stored in intermediate locations. This provides an effective mechanism for selective flattening.

REFERENCES:
patent: 5050091 (1991-09-01), Rubin
patent: 5281558 (1994-01-01), Bamji et al.
patent: 5528508 (1996-06-01), Russell et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5604680 (1997-02-01), Bamji et al.
patent: 5625564 (1997-04-01), Rogoyski
patent: 5629861 (1997-05-01), Kim
Nunes et al. ("A new approach to perform circuit verification using O(n) algorithms", IEEE, Proceedings of the 20th EUROMICRO Conference: System Architecture and Integrations, Sep. 5, 1994, pp. 428-432.
Hedenstierna et al. ("The halo algorithm--an algorithm for hierarchical design of rule checkiing of VLSI circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 2, Feb. 1993, pp. 265-272).
Stevens et al. ("An Integrated Approach for Hierarchical Verification of VLSI Mask Artwork", IEEE Journal of Solid-State Circuits, vol. Sc-20, No. 2, Apr. 1985, pp. 501-509.
Hedenstierna et al. ("The use of inverse layout trees for hierarchical design verification", IEEE International Conference on Computer-Aided Design, ICCAD-88, Nov. 7, 1988, pp. 534-537).
Goering ("Avant! Launches Hercules verification Tool", Electronic Engineering Times, No. 924, p. 100 (1-2), Oct. 21, 1996,.
Martin E. Newell, Daniel T. Fitzpatrick; "Exploiting Structure in Integrated Circuit Design Analysis"; Jan. 26, 1982; Xerox Palo Alto Research Centers and Computer Science Division University of California, Berkeley, 1982 Conference on Advanced Research in VLSI, M.I.T., PP. 84-92.

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