Layout of Vdd and Vss balls in a four layer PBGA

Details Layout of Vdd and Vss balls in a four layer PBGA Layout of Vdd and Vss balls in a four layer PBGA

2001-02-12

2002-09-17

Paladini, Albert W. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C251S315040, C251S315040, C251S315040, C251S315040, C251S315040, C251S315040

Reexamination Certificate

active

06452262

ABSTRACT:

BACKGROUND
This invention generally relates to Ball Grid Array (BGA) packages, and more specifically relates to a new scheme of laying out Vdd (power) and Vss (ground) balls in a four layer BGA package to provide certain advantages over prior art four layer BGA package designs.
An integrated circuit package provides electrical connection from an integrated circuit chip or die to external electrical connections. These external electrical connections may be, for example, connections on a system board or printed circuit board. A Ball Grid Array (BGA) package is one type of integrated circuit package which has become increasingly popular, particularly because, among other benefits, it allows a high density of external connections. BGA technology is a surface mount package technology that uses an array of solder balls to make electrical contact with the system circuit board, as opposed to pins or peripheral leads.
One type of BGA package is a four layer BGA package. A typical four layer BGA package is configured such that layer
1
is a signal layer, layer
2
is a ground layer, layer
3
is a power layer and layer
4
is another signal layer. The signal layers (layers
1
and
4
) provide various signal lines or traces while the ground layer (layer
2
) and power layer (layer
3
) provide a ground plane and a power plane, respectively, each of which is typically formed of a conductive metal, such as copper. While power (Vdd) balls provide electrical paths for providing power from the system board to the die, ground (Vss) balls provide electrical paths for providing ground from the system board to the die.
FIG. 1
illustrates a typical pattern for laying out the power balls
10
and ground balls
12
in a four layer BGA package. As shown, the power balls
10
and ground balls
12
are interspersed in a ball field
14
(with signal balls
15
) around the die
16
. The power balls
10
are connected to the power plane (on layer
3
) through vias, and the ground balls
12
are connected to the ground plane (on layer
2
) through vias. The planes help reduce the inductance of the Vdd and Vss in the package by providing a copper sheet where the current can flow without any obstructions. In fact, in a typical four layer BGA package design, it is essential that a power plane and ground plane be provided in the package to reduce the inductance of the Vss and Vdd paths. Because a power plane must be provided, and is typically provided on layer
3
of a typical four layer BGA package, real estate is consumed in the package that could otherwise be used for routing and for IO's. Additionally, as shown in
FIG. 1
, a typical four layer BGA package provides that ground balls
12
are spaced apart and not paired. As a result of this arrangement, the number of layers which are needed on the system board to route all the pins is not minimized.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide a new scheme for laying out the power (Vdd) balls and ground (Vss) balls in a four layer BGA package.
Another object of an embodiment of the present invention is to eliminate the use of the power plane in a four layer BGA package, thereby providing additional real estate for routing traces and allowing additional IO's to be provided.
Still another object of an embodiment of the present invention is to provide a layout of ground (Vss) balls in a BGA package which reduces the number of layers needed on the system board to route out all the pins.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a BGA package wherein power is provided to the die through power (Vdd) balls which are located in an inner most row of solder balls. Preferably, each power ball is effectively connected to a power ring on layer
1
of the package. By arranging the power balls in an inner most row, it is possible to reduce the distance the electrical signal has to travel to reach the power ring. Hence, a thick short trace may connect each power ball to a via which connects to the power ring on layer
1
.
Preferably, ground is provided to the die through ground (Vss) balls which are dispersed in a ball field around the periphery of the inner most row of power balls. Preferably, the ground balls are paired together, because by pairing the ground balls, it is possible to use only one via for two ground balls on the system board. This reduces the number of layers needed on the system board to route all of the pins and may make it possible, for example, to route more traces on the system board.


REFERENCES:
patent: 5640048 (1997-06-01), Selna
patent: 5714801 (1998-02-01), Yano et al.
patent: 6057596 (2000-05-01), Lin et al.
patent: 6064113 (2000-05-01), Kirkman
patent: 6225702 (2001-05-01), Nakamura

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