Layout of semiconductor memory and content-addressable memory

Details Layout of semiconductor memory and content-addressable memory Layout of semiconductor memory and content-addressable memory

1995-09-28

1997-06-24

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523008, 36518905, G11C 700, G11C 800

Patent

active

056423225

ABSTRACT:
The layout of a semiconductor memory and a content-addressable memory is adaptable for size reduction, high-speed operation and power saving. The layout of a semiconductor memory on a semiconductor chip has a plurality of memory blocks, each of which includes a plurality of memory wards, a main ward line extending from a main decoder through each memory ward, a memory block selection line extending from a subdecoder through each memory block, and a memory ward selection means provided in each memory ward of each memory block. A column of more than one row of memory cells are used to form each memory ward of each memory block, and at least one subward line for simultaneously and totally activating all the memory cells is provided for the row of memory cells.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 5046046 (1991-09-01), Sweha et al.

Affiliated with

Also associated with

Rating

Layout of semiconductor memory and content-addressable memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout of semiconductor memory and content-addressable memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout of semiconductor memory and content-addressable memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-153387