Layout of integrated circuit with very large transistors

Details Layout of integrated circuit with very large transistors Layout of integrated circuit with very large transistors

1991-03-27

1992-05-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307304, 307241, 357 42, H03K 3335, H03K 3353

Patent

active

051110695

ABSTRACT:
An integrated circuit which provides multiple independently accessible low-on-state-resistance switches, using conventional CMOS technology. Charge pumping is used to boost the gate voltage to lower the on-state resistance. The surface of the chip consists primarily of a few very large path transistors. This chip is perferably combined with a power management chip which provides logic outputs, and the large PMOS switches are used for controlling the power supply to various other chips, such as SRAMs.

REFERENCES:
patent: 4931844 (1990-06-01), Zommer
patent: 5030861 (1991-07-01), Hoffman et al.
patent: 5036215 (1991-07-01), Masleid et al.

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