Layout of flash memory and formation method of the same

Details Layout of flash memory and formation method of the same Layout of flash memory and formation method of the same

1998-12-28

2000-05-23

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518533, G11C 1604

Patent

active

060672498

ABSTRACT:
A layout of a flash memory and a formation method of the same are disclosed. The layout includes a plurality of memory cells each having a cell transistor having a cell gate electrode having a floating gate and a control gate, and a source/drain electrode for thereby storing and erasing a data, a selection transistor having two gate electrodes, a common drain electrode between the gate electrodes and a source electrode formed outside the same and having a predetermined channel width larger than two times compared to the channel width of the cell transistor, and the drain electrode and source electrodes which are crossingly formed to each other with respect to the axis of the word lines through which a driving voltage is applied to the gate electrodes for thereby selecting a corresponding memory cell, a pair of cell bit lines connected with the source electrode of the selection transistor and connected in parallel with the drain electrode of the memory cell transistor for inputting/outputting the data to the cell transistor, and a pair of array bit lines connected with a drain electrode of the selection transistor and a peripheral circuit.

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