Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-05-04
2002-10-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S205000, C365S214000
Reexamination Certificate
active
06473324
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to the layout of a sense amplifier configuration for a semiconductor memory having a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, with NMOS and PMOS ok transistors. The sense amplifier configuration also has two driver transistors. The driver transistors extend perpendicularly to the read/write amplifiers and are formed as strips in the form of columns over a plurality of read/write amplifier rows. The sense amplifier configuration further has non-inverted and inverted bit lines extending in the read/write amplifier rows.
Layouts of this type are generally known in semiconductor DRAMs, in each case two driver transistors provide, during the sense operation, a signal for the PMOS transistors of numerous read/write amplifiers and also a signal for the corresponding NMOS transistors of the numerous read/write amplifiers. As the clock frequency of DRAMs increases, in particular the rapid provision of the signals for the sense operation acquires increasing importance. The further the signal is developed in particular during the first read or write access of a cycle, the more quickly the respective sense amplifier node developed by the PMOS transistors reaches its final value. The same applies correspondingly to the signal for the and the nodes of the read/write amplifiers that are developed by the NMOS transistors.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a layout of a sense amplifier with accelerated signal evaluation, which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the signal evaluation in the sense amplifiers is accelerated and, for example, the acceleration of the development of the side driven by the PMOS transistors.
With the foregoing and other objects in view there is provided, in accordance with the invention, a layout of a sense amplifier configuration for a semiconductor memory. The layout of the sense amplifier configuration contains a plurality of read/write amplifiers extending as strips in rows one under another and has NMOS and PMOS transistors. Two driver transistors are connected to the read/write amplifiers. The two driver transistors are strip shaped and extend perpendicularly to the read/write amplifiers in a form of columns over the rows of the read/write amplifiers. At least one of the two driver transistors has doping regions disposed between associated NMOS or PMOS transistors of the read/write amplifiers. The at least one of the two driver transistors has a gate formed as a two-strip gate with two strips. Non-inverted and inverted bit lines extend in the rows of the read/write amplifiers.
The object of the invention is achieved by virtue of the fact that at least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers, and in that the gate of the driver transistor is a two-strip gate. The doubling of the width of the driver transistor makes it possible to significantly increase the signal development in the sense amplifier without having to increase the area requirement in a relevant manner. Particularly when the PCS driver transistor is realized according to the invention, a compact structural size is realized in conjunction with distinctly improved driver power.
The insertion of transverse webs between the two gate strips of the driver transistor enables balancing of the signal supply of the PMOS transistors of the read/write amplifiers, optimization of the gate resistance of the driver transistor and, moreover, setting of the gate capacitance of the driver transistor for the NMOS transistors. The same applies correspondingly to the driver transistor for the NMOS transistors. In this way, the speed of the signal development and the noise filtering can be set in a manner optimized in an application-specific manner. The space-saving “dual gate technique” makes it possible, in a simple manner, to provide a plurality of gate transverse webs in each case. It is advantageous for the gate transverse web to extend parallel to the read/write amplifier strip at least in the outer edge region thereof, in order simultaneously to be able to realize additional contact-connection of the gate of the driver transistor in a simple manner.
In accordance with an added feature of the invention, gate transverse webs are provided. The at least one of the two driver transistors has a channel width and the two strips of the two-strip gate are conductively connected to one another by the gate transverse webs over a part of the channel width.
In accordance with another feature of the invention, each of the gate transverse webs extends parallel to a respective one of the read/write amplifiers in a form of a strip at least in an outer edge region thereof.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a layout of a sense amplifier with accelerated signal evaluation, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4644637 (1987-02-01), Temple
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 5422853 (1995-06-01), Miyamoto
patent: 6195282 (2001-02-01), Foss
patent: 6195302 (2001-02-01), Hardee
patent: 6249471 (2001-06-01), Roy
Fischer Helmut
Markert Michael
Schneider Helmut
Schöniger Sabine
Auduong Gene N.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
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