Layout method of wiring pattern for semiconductor integrated cir

Details Layout method of wiring pattern for semiconductor integrated cir Layout method of wiring pattern for semiconductor integrated cir

1997-11-03

1998-09-01

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

058019600

ABSTRACT:
A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.

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Greenberg et al. ("Minimizing channel density with movable terminals", IEEE Comput. Soc. Press, Proceedings of the Third Great Lakes Symposium on VLSI Design Automation of High Performance VLSI Systems, 5 Mar. 1993, pp. 1-5).
Upton et al. ("Integrated placement for mixed macro cell and standard cell designs", IEEE, Proceedings of the 27th ACM/IEEE Design Automation Conference, 24 Jun. 1990, pp. 32-35).

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