Layout method of semiconductor memory and content-addressable me

Details Layout method of semiconductor memory and content-addressable me Layout method of semiconductor memory and content-addressable me

1996-12-23

1998-10-06

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523008, 365200, 36518905, G11C 800, G11C 700

Patent

active

058187863

ABSTRACT:
The layout of a semiconductor memory and a content-addressable memory is adaptable for size reduction, high-speed operation and power saving. The layout of a semiconductor memory on a semiconductor chip has a plurality of memory blocks, each of which includes a plurality of memory words, a main word line extending from a main decoder through each memory word, a memory block selection line extending from a subdecoder through each memory block, and a memory word selection means provided in each memory word of each memory block. A column of more than one row of memory cells are used to form each memory word of each memory block, and at least one subword line for simultaneously and totally activating all the memory cells is provided for the row of memory cells.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 5046046 (1991-09-01), Sweha et al.
patent: 5642322 (1997-06-01), Yoneda

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