Layout method of a comparator array for flash type analog to...

Details Layout method of a comparator array for flash type analog to... Layout method of a comparator array for flash type analog to...

2005-05-10

2005-05-10

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S158000

Reexamination Certificate

active

06891494

ABSTRACT:
The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2n −Ivoltages and being arranged to be folded; a comparator array including (2n−1) comparators for comparing voltage differences between the respective 2n −Ivoltages and an analog input signal to generate a digital thermometer code having (2n−1) bits and an encoder for encoding the digital thermometer code having (2n−1) bits to generate an n-bit digital signal. The layout method of the flash type analog to digital converting circuit comprises arranging the comparators such that the comparators of (2n−1)thcomparator to (2n/2)thcomparator are arranged in order and the comparators of (2n/2−1)thcomparator to a first comparator are arranged in reverse fashion between the comparators of the (2n−1)thcomparator to the (2n/2)thcomparator; and arranging the comparators such that the neighboring comparators adjacent to the respective (2n−1) comparators remain at to the same state when the (2n−1)thcomparator to the (2n/2)thcomparator transit to different states respectively. Therefore, increasing of an offset voltage due to the effects of the neighboring comparators is prevented without increasing a layout area size.

REFERENCES:
patent: 5416484 (1995-05-01), Lofstrom
patent: 5554989 (1996-09-01), Kumamoto et al.
patent: 6014097 (2000-01-01), Brandt

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