Layout method for semiconductor integrated circuit and layout ap

Details Layout method for semiconductor integrated circuit and layout ap Layout method for semiconductor integrated circuit and layout ap

1995-07-21

1998-04-28

Louis-Jacques, Jacques H.

Boots, shoes, and leggings

H01L 2160, H01L 2174

Patent

active

057453748

ABSTRACT:
There is disclosed a layout method for a semiconductor integrated circuit for use in design by a symbolic layout which expresses a configuration of the semiconductor integrated circuit by symbols. The layout method comprises the steps of extracting a mask layout to be processed, changing dimensions of a symbolic layout included in the mask layout, replacing transistor symbols included in the mask layout with symbols having diffusion layer terminals each having a constant length in the channel width direction and not having extent in the channel length direction, shortening a length of wiring included in the mask layout in the channel width direction of the transistor, and compacting the mask layout in the channel length direction of the transistor.

REFERENCES:
patent: 5018074 (1991-05-01), Griffith et al.
patent: 5369596 (1994-11-01), Tokumaru
patent: 5388054 (1995-02-01), Tokumaru
patent: 5535134 (1996-07-01), Cohn et al.
patent: 5541025 (1996-07-01), Oi et al.
J. Dao, et al., "A compaction Method for Full Chip VLSI Layouts", Proc. 30th Design Automation Conference, Jan. 1993, pp. 407-412.
"An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints"; Yuh-Zen Liao, and C.K. Wong; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; Apr. 1983, pp. 62-69.
"Improved Compaction by Minimized Length of Wire"; W. L. Schiele; Proceedings of the 20th Design Automation Conference; Munich, Germany; pp. 121-127, Jan. 1983.
"Kahlua: A Hierarchical Circuit Disassembler"; Bill Lin, and A. Richard Newton; 24th ACM/IEEE Design Automation Conference; Jun. 1987, pp. 311-317 .

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