Boots – shoes – and leggings
Patent
1994-09-02
1995-05-30
Trans, Vincent N.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1750
Patent
active
054208009
ABSTRACT:
A method is provided for designing a semiconductor integrated circuit device with optimized shape of blocks to minimize the size of the chip containing the circuit. Design restrictions on the shape and position of each block are determined according to the density of temporary paths for electrical connections between blocks and the shape of each side of each block is optimized within the restrictions. The internal layout of each block is then optimized according to the restrictions.
REFERENCES:
patent: 4500963 (1985-02-01), Smith et al.
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4613941 (1986-09-01), Smith et al.
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4686629 (1987-08-01), Noto et al.
patent: 4752887 (1988-06-01), Kuwahara
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4835705 (1989-05-01), Fujino et al.
patent: 4910680 (1990-03-01), Hiwatashi
patent: 4964057 (1990-10-01), Yabe
patent: 5046017 (1991-09-01), Yuyama et al.
patent: 5047949 (1991-09-01), Yamaguchi et al.
Fukui, M., et al., "SMILE: A Hierarchical Layout System for Building Block LSI", International Journal of Computer Aided VLSI Design 1, 281-303 (1989).
Matsushita Electric - Industrial Co., Ltd.
Trans Vincent N.
LandOfFree
Layout method for a semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layout method for a semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout method for a semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-367562