Layout method for a chip

Details Layout method for a chip Layout method for a chip

2011-04-12

2011-04-12

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S113000, C716S123000, C716S126000, C716S136000

Reexamination Certificate

active

07926017

ABSTRACT:
A layout method is provided, adaptable to place cell on a chip. Firstly, a chip area is assigned for a floor plan. A global reservation deployment process is then performed to define a plurality of room units to be uniformly distributed on the chip area. Cells are placed on the chip based on the floor plan. The chip area is categorized into at least a high frequency region and a low frequency region according to operation frequencies of the placed cells thereon. A frequency based reservation deployment process is then performed to move one or more room units distributed in the low frequency region toward the high frequency region. A local cell replacement process, a routing and timing analysis are performed. If hotspots are induced, room units around the hotspots are redistributed, and then the steps of local cell replacement, routing and timing analysis are repeated.

REFERENCES:
patent: 5847965 (1998-12-01), Cheng
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 7107568 (2006-09-01), Cronquist

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