Data processing: structural design – modeling – simulation – and em – Structural design
Reexamination Certificate
1997-02-19
2001-10-23
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Structural design
C703S013000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06308143
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout input apparatus, a layout input method, a layout verification apparatus and a layout verification method.
2. Description of the Related Art
In recent years, the degree of integration of semiconductor integrated circuits is increasing, and their operation speed is becoming higher. Under this circumstance, various large-scale systems are being realized by a semiconductor integrated circuit formed on a single chip, which greatly contributes to the miniaturization and decrease in cost of such systems.
However, in order to produce a semiconductor integrated circuit whose minimum size is reduced to a quarter micron or less, significant capital investment is required. Furthermore, it is becoming difficult to enhance production yield with the increase in chip area and high integration of a semiconductor integrated circuit. Therefore, it may cost lower to realize a large-scale system by combining a plurality of relatively large semiconductor integrated circuits produced by a conventional process than to realize a large-scale system on a single chip.
A mounting technique as shown in
FIGS. 34A through 34D
has been proposed for the purpose of reducing the production cost and mounting area of a semiconductor integrated circuit. According to this mounting technique, a semiconductor chip with a first LSI formed thereon (first LSI chip) and a semiconductor chip with a second LSI formed thereon (second LSI chip), as shown in
FIG. 34A
, are mounted in a single package in such a manner that they are superposed on top of the other. For example, a semiconductor integrated circuit chip with a central processing unit (CPU) formed thereon is used as the first LSI chip, and a semiconductor integrated circuit chip with a static RAM (SRAM) is used as the second LSI chip.
Conventional semiconductor integrated circuits are composed of a number of semiconductor devices formed on one principal surface of a semiconductor substrate (semiconductor chip) and wirings connecting the devices to each other. According to the Flip & Stack mounting technique, two semiconductor chips are placed in such a manner that their surfaces on which semiconductor integrated circuits are formed face each other, as shown in
FIGS. 34B through 34D
. Terminal pins (not shown) of a package are electrically connected through bonding wires to a bonding pad provided on the periphery of the first LSI chip. Input/output (I/O) terminals of the second LSI chip are connected to I/O terminals for Flip & Stack mounting provided on the first LSI chip. Such a connection requires the first LSI chip and the second LSI chip to be provided with electrical connecting portions which have a “mirror inversion” relationship, as shown in FIG.
34
A.
As described above, according to the conventional Flip & Stack mounting technique, two semiconductor integrated circuits which are different in function and use, such as a CPU and an SRAM, are used as the first and second LSIs. The layouts of these two semiconductor integrated circuits are independently designed by a conventional layout input method, after the coordinates of the connecting portions which have a mirror inversion relationship are defined.
However, the conventional layout input method does not allow the layouts of two LSIs to be designed simultaneously. This makes it difficult to determine optimum layouts, resulting in an increase in the time required for designing layouts. In addition, the layout verification is required to be conducted independently with respect to two LSIs. Therefore, the number of steps of forming net lists for an individual LSI increases. Furthermore, the connection between two LSIs is manually checked, which increases verification time and decreases reliability.
SUMMARY OF THE INVENTION
The layout input apparatus of the present invention, includes: an input section for inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit; a control section for performing a predetermined coordinate transformation with respect to the second coordinate information; and a storage section for storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit.
In one embodiment of the present invention, the control section performs the predetermined coordinate transformation when the second coordinate information is stored in the storage section.
In another embodiment of the present invention, the control section performs the predetermined coordinate transformation in response to the input of the second coordinate information.
In another embodiment of the present invention, the predetermined coordinate transformation includes a symmetrical transformation with respect to a predetermined axis.
In another embodiment of the present invention, the predetermined coordinate transformation further includes a parallel movement along a predetermined direction.
In another embodiment of the present invention, a first coordinate system for the first layout data is different from a second coordinate system for the second layout data.
In another embodiment of the present invention, each of the first coordinate system and the second coordinate system has an X-axis and a Y-axis, and an origin in the first coordinate system is shifted from an origin in the second coordinate system by a predetermined X-offset in a direction of the X-axis and by a predetermined Y-offset in a direction of the Y-axis.
In another embodiment of the present invention, the predetermined Y-offset is 0.
In another embodiment of the present invention, the predetermined X-offset is 0 and the predetermined Y-offset is 0.
According to another aspect of the present invention, a layout input method includes the steps of: inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit; performing a predetermined coordinate transformation with respect to the second coordinate information; and storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit.
According to another aspect of the present invention, a layout verification apparatus includes: a storage section for storing first layout data representing a layout of a first semiconductor integrated circuit, second layout data representing a layout of a second semiconductor integrated circuit, and connection information defining a position of a connecting portion connecting the first semiconductor integrated circuit to the second semiconductor integrated circuit; and a control section for specifying a first position in the first layout data corresponding to the position of the connecting portion and a second position in the second layout data corresponding to the position of the connecting portion, based on the connection information, and verifying the layouts of the first and second semiconductor integrated circuits, considering that the first position is connected to the second position.
In one embodiment of the present invention, the position of the connecting portion, the first position, and the second position are represented by an identical coordinate.
In another embodiment of the present invention, the first layout data includes a plurality of first layer
Matsushita Electric - Industrial Co., Ltd.
Phan Thai
Renner Otto Boisselle & Sklar
Teska Kevin J.
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