Layout for stable high speed semiconductor memory device

Details Layout for stable high speed semiconductor memory device Layout for stable high speed semiconductor memory device

1987-02-17

1989-01-03

Hecker, Stuart N.

Static information storage and retrieval

Format or disposition of elements

365 63, 365230, 365189, G11C 502

Patent

active

047962240

ABSTRACT:
In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.

REFERENCES:
patent: 4586171 (1986-04-01), Fujishima
patent: 4648077 (1987-03-01), Pinkham et al.
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4695978 (1987-09-01), Itakura
patent: 4700328 (1987-10-01), Burghard
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4701885 (1987-10-01), McElroy

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