Layout for semiconductor memory including multi-level sensing

Details Layout for semiconductor memory including multi-level sensing Layout for semiconductor memory including multi-level sensing

1999-05-20

2001-02-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S230030

Reexamination Certificate

active

06188596

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and in particular, to organization and layout thereof.
2. Description of the Related Art
Semiconductor memories are characterized by regular repetition of memory cells, which are typically organized in an hierarchical addressing topology. Each memory cell is associated with a unique address that typically identifies a particular row and column in a matrix. A group of memory cells is selected by activating a row line (or in some configurations, a word line) to which cells of the group are connected. This enables each of the memory cells so selected, when in a read access mode, to drive its associated column line (or in some configurations, bit-line) in a manner corresponding to the data stored therein. Alternatively, when in a write access mode, each of the selected memory cells is enabled to receive data conveyed on the bit-line to the memory cell.
There are many ways to arrange a bit-line configuration and an associated read circuit. One well-known technique uses a cross-coupled sense amplifier. Typically, a pair of bit-lines couple complementary sides plural of cross-coupled memory cells to a differential amplifier that senses a slight difference in voltage between the two bit-lines and drives a stable, full-level (or full-voltage-swing) signal that may then be further decoded and eventually routed to an output signal path. Sense amplifier circuits are typically constructed from a bi-stable circuit block (such as a cross-coupled differential pair of transistors) that is forced into an unstable state before the bit-lines are to be sensed. During sensing, a slight differential input from the bit-lines pushes the sense amplifier into one of two stable states (e.g., corresponding to a logic “1” or logic “0”). Consequently, conventional sense amplifier circuits can consume significant power while actually sensing the bit-lines.
As memory size increases, fanout and/or downstream signal path impedance tends to increase as bit-lines or sense amplifier output paths span larger proportions of overall layout area. Accordingly, typical speed vs. power trade-offs tend to force larger device sizes, greater power consumption, and/or slower access times. Array partitioning and localized amplification have been used to reduce power consumption in Static Random Access Memories (SRAMs) and thereby improve SRAM speed/power ratios. Two-level sensing has even been used (see e.g., Flannagan et al., 8-ns CMOS 64K×4 and 256K×1 SRAMs, IEEE
Journal of Solid State Circuits
, Vol. 25, No. 5, October 1990, pp. 1049-54) with small signal excursions for power reduction.
Nonetheless, memory configurations are desired which even in combination with array subdivision or small-signal techniques may further reduce power consumption or increase access speed. Indeed memory configurations are desired which better optimize area/speed/power tradeoffs. For memory configurations where large numbers of sense amplifiers are defined within submodules or banks and where large numbers of columns are typically read out simultaneously (e.g., in cache memory or embedded memory applications), area/speed/power tradeoffs associated with submodule- or bank-resident sense amplifiers, or more generally with read data paths, are important. Improved memory configurations are desired.
SUMMARY OF THE INVENTION
Accordingly, a memory module configuration has been developed, which employs multi-level sensing, low-voltage-swing differential signal paths, and array layout techniques to better optimize area/speed/power tradeoffs. In some configurations two-level sensing is employed with secondary sense amplifiers positioned toward a middle of the memory module with memory banks or submodules positioned therearound. Primary sense-amplifiers in the submodules or banks sense differential signals on local bit-lines spanning the corresponding submodule or bank and drive a low-voltage-swing differential signal onto global bit-lines that span a subset of the submodules or banks. The global bit-lines are sensed by secondary sense amplifiers that drive data outputs across a subset of the submodules or banks toward output circuits. In some configurations the memory module is divided into upper and lower portions with upper global bit-lines spanning the upper portion and lower global bit-lines spanning the lower portion. Corresponding upper and lower global bit-lines are disjoint and are sensed by corresponding upper and lower secondary sense amplifiers. By this arrangement, the minimum to maximum variation in access time between the different rows of the module is reduced. Moreover, smaller drivers and lower power is achieved by use of such a two-level arrangement. In particular, area reductions and power reductions are achieved for submodule- or bank-resident primary sense amplifiers.
In configurations, such as cache memory, where large numbers (e.g., 512 or more) of columns are read simultaneously, area and power reductions in correspondingly large numbers of primary sense amplifiers (e.g., 512 or more) per submodule or bank are substantial. For example, in some on-board cache memory module configurations in accordance with the present invention, power dissipation has been reduced by approximately 50% while maintaining high speed operation at processor clock speeds and with a 64-byte read data path. Memory module areas have also been reduced by approximately 10%.
In one embodiment in accordance with the present invention, a semiconductor memory includes upper and lower groups of submodules and disjoint upper and lower bit-line pairs. Each submodule includes an array of memory cells and primary sense amplifiers. The upper bit-line pairs span the upper group of submodules and the lower bit-line pairs span the lower group of submodules. The primary sense amplifiers are coupled to drive a differential signal onto corresponding of the upper or lower bit-line pairs and are placed between the upper and lower groups of submodules. Upper ones of the secondary sense amplifiers are coupled to corresponding of the upper bit-line pairs, and lower ones of the secondary sense amplifiers are coupled to corresponding of the lower bit-line pairs.
In a semiconductor memory embodiment in accordance with the present invention, a data path includes a first differential bit-line pair, a first primary sense amplifier, and a first secondary sense amplifier. The first differential bit-line pair spans plural memory cells of a first bank including a first memory cell. The first primary sense amplifier is coupled between the first differential bit-line pair and coupled to supply a first differential output on a second differential bit-line pair spanning a first group of banks including the first bank. The first secondary sense amplifier is coupled between the second differential bit-line pair and coupled to supply a full-voltage swing output on a data line, wherein the data line spans a second group of banks. In a further variation, the data path also includes a third differential bit-line pair, a second primary sense amplifier, and a second secondary sense amplifier. The third differential bit-line pair spans plural memory cells of a second bank including a second memory cell. The second primary sense amplifier is coupled between the third differential bit-line pair and coupled to supply a second differential output on a fourth differential bit-line pair spanning a second group of banks disjoint from the first group of banks and including the second bank. The second secondary sense amplifier is coupled between the fourth differential bit-line pair and coupled to supply a full-voltage swing output on the data line.
In another embodiment in accordance with the present invention, a method of reducing a difference between minimum and maximum delay paths in a semiconductor includes the following: providing plural submodules each including an array of memory cells and primary sense amplifiers coupled to respective ones of the memory cells by local bit-lines; s

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