Layout for pull-up/pull-down devices of off-chip driver

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure

Reexamination Certificate

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Details

C327S112000

Reexamination Certificate

active

06184749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the wiring layout of an integrated circuit. More particularly, the present invention relates to the wiring layout for the pull-up and pull-down devices of an off-chip driver.
2. Description of the Related Art
Due to the rapid increase in the level of integration, compact and lightweight electronic products have emerged. To catch up with these highly functional products, the layout of a chip carrier for supporting a silicon chip in a package and the layout of a printed circuit board (PCB) for assembling electronic components and other circuit boards have been improved. Because the pin-counts of electronic devices increase with the level of integration, the number of bonding pads on a circuit board must increase correspondingly. Consequently, density of wires on a circuit board must also increase. In addition, due to the high-density layout and miniaturization of signaling lines, distance of separation between neighboring bonding pads must be greatly reduced as well.
FIG. 1
is the layout and wiring connections of pull-up and pull-down devices in a conventional off-chip driver (OCD).
The off-chip driver (OCD) as shown in
FIG. 1
includes bonding pads
11
and
12
, pull-up drivers
21
and
22
, pull-down drivers
23
and
24
, pull-up signaling lines
31
and
32
and pull-down signaling lines
33
and
34
. The pull-up driver
21
and the pull-down driver
23
provide pull-up voltage and pull-down voltage to the bonding pad
11
, respectively. Similarly, the pull-up driver
22
and the pull-down driver
24
provide pull-up voltage and pull-down voltage to the bonding pad
12
, respectively. The pull-up driver
21
and the pull-down driver
23
are located on opposite sides (for example, the upper and lower sides as shown in
FIG. 1
) of the bonding pad
11
. The pull-up driver
22
and the pull-down driver
24
are also located on the upper and lower sides of the bonding pad
12
, respectively. In other words, both pull-up drivers
21
and
22
are on the same side above the bonding pads
11
and
12
while both pull-down drivers
23
and
24
are on the same side below the bonding pads
11
and
12
.
The pull-up signal lines
31
and
32
are connected to the pull-up driver
21
and the pull-up driver
22
through conductive lines
41
and
42
, respectively. Hence, a pull-up voltage is provided to each active device
51
inside the pull-up driver
21
and each active device
52
inside the pull-up driver
22
. The active devices
51
and
52
are metal-oxide-semiconductor (MOS) transistors, for example. Note that the conductive line
41
branches off from the pull-up signal line
31
, runs along the side of the pull-down driver
23
, the bonding pad
11
and the pull-up driver
21
and finally enters the pull-up driver
21
. The conductive line
42
branches off from the pull-up signal line
32
, runs along the side of the pull-up driver
22
and finally enters the pull-up driver
22
. The pull-down signal lines
33
and
34
are connected to the pull-down driver
23
and the pull-down driver
24
through conductive lines
43
and
44
, respectively. Hence, a pull-down voltage is provided to each active device
53
inside the pull-down driver
23
and each active device
54
inside the pull-down driver
24
. Note that the conductive line
44
branches off from the pull-down signal line
34
, runs along the side of the pull-up driver
22
, the bonding pad
12
and the pull-down driver
24
and finally enters the pull-down driver
24
. The conductive line
43
branches off from the pull-up signal line
33
, runs along the side of the pull-down driver
23
and finally enters the pull-down driver
23
.
The number of bonding pads is not restricted to just two. Obviously, for more than two bonding pads, the increase in the number of pull-up drivers is equal to the number of pull-down drivers.
However, as the number of bonding pads increases, extra space must be set aside for laying the pull-up and pull-down conductive lines for connection with the pull-up and pull-down drivers. Hence, overall layout area will increase.
In addition, as the distance of separation between a pull-up driver or a pull-down driver and bonding pad increases, overall length of the conductive lines leading into the pull-up driver or the pull-down driver also increases. Hence, signal transmission time increases.
Furthermore, as the level of integration of integrated circuits continues to decrease, not only do the dimensions of each electronic device decrease, but area for laying conductive lines shrink as well. Consequently, how to reduce the area necessary for laying connection lines is an important issue in the semiconductor industry.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a layout for the pull-up and pull-down devices of an off-chip driver so that the area necessary for laying the connection lines can be reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a layout of the pull-up and pull-down devices in an off-chip driver. The off-chip driver includes a first and a second bonding pads, a first and a second pull-up driver, a first and a second pull-down driver, a first and a second pull-up signal line, and a first and a second pull-down signal line. The second bonding pad is placed next to the first bonding pad. The first pull-up driver is formed below the first bonding pad for providing a first pull-up voltage to the first bonding pad. The first pull-down driver is formed on the right side of the first pull-up driver for providing a first pull-down voltage to the first bonding pad. The second pull-up driver is formed above the second bonding pad for providing a second pull-up voltage to the second bonding pad. The second pull-down driver is formed on the left side of the second pull-up driver for providing a second pull-down voltage to the second bonding pad. The first pull-up conductive line branches from the first pull-up signal line just below the first pull-up driver and enters the first pull-up driver. The first pull-up signal line provides a first pull-up voltage to the active devices inside the first pull-up driver so that the first pull-up driver is driven to a first high potential level. The first pull-down conductive line branches from the first pull-down signal line just below the first pull-down driver and enters the first pull-down driver. The first pull-down signal line provides a first pull-down voltage to the active devices inside the first pull-down driver so that the first pull-down driver is pulled down to a first low potential level. The second pull-up conductive line branches from the second pull-up signal line just above the second pull-up driver and enters the second pull-up driver. The second pull-up signal line provides a second pull-up voltage to the active devices inside the second pull-up driver so that the second pull-up driver is driven to a second high potential level. The second pull-down conductive line branches from the second pull-down signal line just above the second pull-down driver and enters the second pull-down driver. The second pull-down signal line provides a second pull-down voltage to the active devices inside the second pull-down driver so that the second pull-down driver is pulled down to a second low potential level. The first pull-up driver and the first pull-down driver can interchange positions. The same applies to the second pull-up driver and the second pull-down driver.
The layout of pull-up and pull-down devices in an off-chip driver according to this invention is capable not only of simplifying the layout, but also of reducing the layout area. Moreover, even when the distance of separation between the pull-up driver and the pull-down driver from their respective bonding pads is large, additional layout area is unnecessary. In addition, since the layout method can shorten overall length of conductive lin

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